电子密码锁的设计外文翻译

外文文献译文设计(论文)题目:电子密码锁的设计专业与班级:测控技术与仪器0602班学生姓名:于良指导教师:周彬2007年3月18日IntroductionofAT89C51Description:TheAT89C51isalow-power,high-performanceCMOS8-bitmicrocomputerwith4KbytesofFlashprogrammableanderasablereadonlymemory(PEROM).ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindustry-standardMCS-51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithFlashonamonolithicchip,theATMELCo.’sAT89C51isapowerfulmicrocomputerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.Features:·CompatiblewithinstructionsetofMCS-51products·4Kbytesofin-systemreprogrammableFlashmemory·Endurance:1000write/erasecycles·Dataretentiontime:10years·Fullystaticoperation:0Hzto24MHz·Three-levelprogrammemorylock·128×8-bitinternalRAM·32programmableI/Olines·Two16-bitTimer/Counters·Sixinterruptsource·Programmableserialchannel·Low-poweridleandPower-downmodes·On-chiposcillatorandclockcircuitry·Full-duplexUARTserialportinterruptline·DualDataPointerRegisterFunctionCharacteristicDescription:TheAT89C51providesthefollowingstandardfeatures:4KbytesofFlashmemory,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportand1interruptsystemtocontinuefunctioning.ThePower-downModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset.The8051microcontrollerisanindustrystandardarchitecturethathasbroadacceptance,wide-rangingapplicationsanddevelopmenttoolsavailable.Therearenumerouscommercialvendorsthatsupplythiscontrollerorhaveitintegratedintosometypeofsystem-on-a-chipstructure.BothMRCandIAμEchosethisdevicetodemonstratetwodistinctlydifferenttechnologiesforhardening.TheMRCexampleofthisistousetemporallatchesthatrequirespecifictimingtoensurethatsingleeventeffectsareminimized.TheIAμEtechnologyusesultralowpower,andlayoutandarchitectureHBDdesignrulestoachievetheirresults.ThesearefundamentallydifferentthantheapproachbyAeroflex-UnitedTechnologiesMicroelectronicsCenter(UTMC),thecommercialvendorofaradiation–hardened8051,thatbuilttheir8051microcontrollerusingradiationhardenedprocesses.Thisbroadrangeoftechnologywithinonedevicestructuremakesthe8051anidealvehicleforperformingthistechnologyevaluationPinDescription:·VCC:Supplyvoltage·GND:Ground·Port0:Port0isan8-bitopen-drainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.Port0mayalsobeconfiguredtobethemultiplexedloworderaddress/busduringaccessestoexternalprogramanddatamemory.InthismodeP0hasinternalpullups.Port0alsoreceivesthecodebytesduringFlashprogramming,andoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.·Port1:Port1isan8-bitbidirectionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.2·Port2:Port2isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorywhichuses16-bitaddresses(MOVX@DPTR).Inthisapplication,itusesstronginternalpullupswhenemitting1s.Duringaccessestoexternaldatamemorywhichuses8-bitaddresses(MOVX@RI).Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.·Port3:Port3isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sourcefourTTLinputs.WhentheP3Iwrite1after,theyareinternalpull-upishigh,andusedasinput.Asinput,duetotheexternalpull-downforthelow,P3portoutputcurrent(ILL)Thisisduetopull-up'ssake.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelow:Port3alsoreceivessomecontrolsignalsforFlashprogrammingandverification.·RST:Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.·ALE/PROG:AddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(PROG)duringFlashprogramming.InnormaloperationALEisemittedata3constantrateof1/6theoscillatorfrequency,andmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskip