XAUI-interface---Introduction-to-XAUI

XAUIinterface-IntroductiontoXAUIinWhitePapersXAUI,the10GigabitAttachmentUnitInterface,isatechnicalinnovationthatdramaticallyimprovesandsimplifiestheroutingofelectricalinterconnections.DevelopedbytheIEEE802.3ae10GigabitEthernetTaskForce,XAUIdelivers10Gb/sofdatathroughputusingfourdifferentialsignalpairsineachdirection.Itscompactnatureandrobustperformancemakesitidealforchip-to-chip,board-to-board,andchiptoopticsmoduleapplications.SERDES,ASIC,FPGA,andopticalmodulevendorsareallintroducingproductswithXAUIinterfaces.Industryeffortsareunderwayas“plugfest”eventsareheldtoensurethatvendors’offeringsareinteroperable.Thebroadofferingcombinedwithon-goinginteroperabilitytestingisdrivingXAUItobecometheuniversal10Gb/sinterface.ThiswhitepaperisdesignedtoprovideageneraloverviewoftheXAUIinterface(pronounced“zowie”),whichispartofthe10GigabitEthernetstandard.Detailsofthetechnologyarefoundinclauses47and48ofthe10GbEthernetstandard(IEEE802.3ae).XAUIArchitectureUndertheInternationalStandardsOrganization’sOpenSystemsInterconnection(OSI)model,EthernetisfundamentallyaLayer2protocol.AnEthernetPHYsicallayerdevice(PHY),whichcorrespondstoLayer1oftheOSImodel,connectsthemedia(opticalorcopper)totheMAClayer,whichcorrespondstoOSILayer2.The802.3aespecificationdefinestwoPHYtypes:theLANPHYandtheWANPHY.TheWANPHYhasanextendedfeaturesetaddedontothefunctionsofaLANPHY.EthernetarchitecturefurtherdividesthePHY(Layer1)intoaPhysicalMediaDependent(PMD)andaPhysicalCodingSublayer(PCS).ThetwotypesofPHYsaresolelydistinguishedbythePCS.Figure1givesagraphicaloverviewofthearchitecturalcomponentsoftheLAN/WANPHY.BetweentheMACandthePHYistheXGMII,or10GigabitMediaIndependentInterface.TheXGMIIprovidesfullduplexoperationatarateof10Gb/sbetweentheMACandPHY.Eachdirectionisindependentandcontainsa32-bitdatapath,aswellasclockandcontrolsignals.Intotaltheinterfaceis74bitswide.WhileXGMIIprovidesa10Gb/spipeline,theseparatetransmissionofclockanddatacoupledwiththetimingrequirementtolatchdataonboththerisingandfallingedgesoftheclockresultsinsignificantchallengeinroutingthebusmorethantherecommendedshortdistanceof7cm.Forthisreason,chip-to-chip,board-to-boardandchip-to-opticalmoduleapplicationsarenotpracticalwiththisinterface.Consequently,theXGMIIbusputsmanylimitationsonthenumberofportsthatmaybeimplementedonasystemlinecard.Toovercometheseissues,the10GigabitEthernetTaskForcedevelopedtheXAUIinterface.XAUIisafullduplexinterfacethatusesfour(4)self-clockedserialdifferentiallinksineachdirectiontoachieve10Gb/sdatathroughput.Eachseriallinkoperatesat3.125Gb/stoaccommodatebothdataandtheoverheadassociatedwith8B/10Bcoding.Theself-clockednatureeliminatesskewconcernsbetweenclockanddata,andextendsthefunctionalreachoftheXGMIIbyapproximatelyanother50cm.ConversionbetweentheXGMIIandXAUIinterfacesoccursattheXGXS(XAUIExtenderSublayer).AsseeninFigure2,theXGMIIinterfaceisorganizedinto4lanesof8bits.AtthesourcesideoftheXAUIinterfacebytesonagivenlaneaswellasthetimingclockareconvertedwithintheXGXSintoan8B/10Bencodeddatastream.Eachdatastreamistransmittedacrossasingledifferentialpairrunningat3.125Gb/s.Atthedestinationsideoftheinterconnecttheclockisrecoveredfromtheincomingdatastream,itisdecodedandthenmappedbacktothe32bitXGMIIformat..Thus,the74pinwideXGMIIinterfaceisreducedtoaXAUIinterfaceconsistingof8differentialpairor16pins.Furthermore,thesourcesynchronousclockingschemeallowsXAUItocrossclockdomains,whicheliminateselaboratetimingcorrectionwithinthesystem.XAUI-ASelf-ManagedInterfaceTheXAUIemploysthesamerobust8B/10Btransmissioncodeas1000BASE-X.With8b/10bcoding,therearemorethanenoughcodepossibilitiesformappingan8-bitword.Someoftheextracodegroupsareusedforcontrolsignaling;suchasstartofframe,endofframe,channelidle,linkconfigurationsandsoon.ControlwordsareusedduringtheInter-PacketGap(IPG)timeandduringidleperiodstocontinuouslyallowtheinterfacetomaintainwordandlaneallignment.Thisisdonewithnoupperlayersupportrequirement,andallowsXAUItofunctionasaself-managedinterface.Framesynchronizationandlanealignmentisessentiallyatwo-stepprocess.Codegroupsynchronizationisachievedoneachlaneuponreceptionofthreeorderedsetsforthelane.Oneeasilyrecognizablepatternscalledcomma/K/enablestheXAUIreceivertoattainframealignmentontheincomingbitstream.Eachlaneadjustsforproperalignmenttothe/K/wheneveritappears.However,eachserialtransmissionlaneoperatesindependentlyandcanoftencomeoutofalignmentwithrespecttooneanother.AsshowninFigure3,lanealignmentisaccomplishedbyuseofacontrolworddefinedforalignment,referredtoas/A/.TheXAUIlineprotocoldefinesspecifictimesduringtheIPGwhenan/A/wordshouldbepassedonallfourlanessimultaneously.Thereceivingconnectionusesthesewordstocorrectforlane-to-laneskewcommoninmostconnections.TheXAUIinterfacecanlanealignwithupto40bits(12.8ns)ofskewbetweenlanes,allowingforsignificantflexibilityinboarddesign.Furthermore,XAUIcompensatesfordifferencesinclockdomainsthatoftenexistbetweeneachsideofthelink.Bymonitoringthedifferencebetweenincomingandoutgoingdatarates,eachXAUIconnectioncanaddordeletespecificcontrolwordsintheIPG,referredtoas/R/tobalancet