HV-Process-and-Device高压工艺与器件

HVProcessandDeviceTD-HVAgendaHighvoltageproductapplicationHVTechnologyintroductionHVvoltagestandarddevice0.5um5V/40VMixed-signalTechnologyFeatures0.5um5V/40VMixed-signalDesignFlexibility0.5umHVMixed-SignalProcessFlow&ModulesIssueindevelopmentHighvoltageproductapplicationNO.OperationVoltageMainApplication1600V~700VHVSwitch,PFC,PowerConverter,ACmotorcontrol240V~200VDriver(coverPDPdriver),PowerConverter,MotorDriver3≤40VPowerConverter,PowerProtection,LDO,PowerCharger,MotorDriver,Buffer(DataDriver),Regulator,displaydriver,ink-jetprinterHVTechnologyintroduction•E=V/d•E1E2E3P+N+d1VE1P+N-d2VE2d3P-N-VE3PNjunction:)11)(2(0DArNNqVddHVTechnologyintroductionJunctionTerminationTechnologyFieldplate(MFP-MetalfieldplateandRFP-resistivefieldplate)FieldlimitingRing-FLRRESURF(ReducedSURfaceField)DrainHNWN+N+PsubSourceGateFOXHPWN-/P-HighvoltageStandardDeviceDDDStructureHVMOS(for8~12v)N+N+N+NDDPOLYFOXP-subDrainSourceN+ODCOFOXNDDNote:NDDformationthroughNplustwiceimplant,onlyforbigdimensionprocessHighvoltageStandardDeviceNDDN+N+N+NDDPOLYFOXFOXP-subDrainSourceN+ODCO16VDDD+OffsetHVMOS(for12~20v)Note:WithadditionallayerNDDafterpolyHighvoltageStandardDeviceLDMOSHighCurrentoutput;LowdissipationoutputCDMOStechnologyiscreatedbymergingLDMOStechnologyandCMOStechnology.ThemajorityofCDMOSprocessesareusedfordriverandpowerICs.AddingBJToptions,CDMOSwillbecomeBCDprocess.CMOSHighdensitydigitalandanalogCDMOSHighdensitydigitalandanalog;HighCurrentoutput;LowdissipationoutputHighvoltageStandardDeviceHNWN+N+PsubSourcePOLYFOXHPWHNWN+ODCO40VMetalAbove30v(LDMOS-lateraldoublediffusionMOS)40/25V(Vds/Vgs)devicestructureCriticaldimension:1.A:ChannellengthAaffectthebreakdownofpunchthroughandRdson2.B:DriftextensionTOB,BV,Major3.C:TOtoTOspaceC,BV,Major4.D:M1overlapdrainsideTOD,BV,Minor5.E:PolyoverlapFOXE,BV,Minor6.DrainwelltoguardringProvidethefieldisolationandreducethelatchupDrainHNWN+N+PsubSourceGateFOXHPWABCDE0.5um5V/40VMixed-signalTechnologyFeaturesTriplewellLOCOSonP-sub./21mask&25layersexceptalloptions0.5umDPTM5Vbase+5VAnalog+HV40V/25V(Vds/Vgs)LDDandfieldpunchthroughstopimplantforN/PMOSFETUpto3metallayers/ThicktopmetaloptionalTriplewellarchitecturetoisolatenegativebiasBPTEOSforILD/PETEOSforIMDPolycidePoly1forMOSgate/Plainpoly2forPIP/HighRes.Wplugforcontact&viasPECVDOxide/NitrideforpassivationPlugimplantforcontact0.5um5V/40VMixed-signalDesignFlexibility10fundamentaltransistorsand4additionaloptions2PIPcapacitorsforlowandhighvoltageapplication5highresistancepolyresistorsfordifferentapplicationVariousparasiticBJTThickmetalforlowRdsondesignTriplewellarchitecture,allowarbitrarybiasonNchanneldeviceElectricalpolyfusefortrimmingcircuitdesignProvide5VSTDcelllibraryforlogicdesignPhysicalverificationrunsetandPDKonCadenceenvironment0.5umHVMixed-SignalProcessFlow&ModulesIfonlynormal/HVNDep.NMOSLowVtPMOSDep.PMOSThinGOXThickGOXDep.PMOSVtImp.Dep.NMOSVtImp.HVPMOSVtImp.LowVtPMOSImp.NormalVtImp.HVNFImp.PMOS-FieldBaseNMOS-Field/APTSacOXFieldOX/DriveActive②N/P-wellHVN/P-well①DeepN-well0.5umHVMixed-SignalProcessFlow&ModulesPCMPadAl3Via2Al2Via1Al1P+PlugContactLowTCPoly2Res.ONOHighRes.LowTCRes.Poly2N/PSDSpacerN/PLDDPoly1③HighPolyRes.PIPCAP(ONO)①②③iscriticallayerIssueindevelopmentHVNMOSSub-thresholdleakageHVasymmetricNMOSbaselinecondition1.0E-111.0E-101.0E-091.0E-081.0E-071.0E-061.0E-051.0E-0400.511.522.53VgIdSub-thresholdleakinHVNMOSVTcurvecomparedto5vnormalNMOSdevice.Andfromthegraph,thisdevicemusthasaparasiticalNMOSparalleltoHVNMOS,theparasiticalNMOSVTishigherorsmallerthanHVNMOS.IssueindevelopmentAA’BB’CC’DrainSourceGateA:NormalHVNMOSdeviceB&C:Parasiticaldevice.Testcondition:Vd=0.1v,Vsub=Vs=0v,Vgsweepfrom0vto5vABCIssueindevelopment5vP-fieldMOSleakage:AA’BB’AppendixThickmetaloptionforlowRdsonPolyFuseMOSCapacitorsHVdiode/ZenerdiodeLowTCPolyresistorHiPolyresistanceHVPIPcapacitorsPIPcapacitorsHVParasiticBJT5VParasiticBJT18/25v(Vds/Vgs)HVMOSTran.IsolatedHVNMOSTran.40/25V(Vds/Vgs)HVMOSTran.5vIsolatedNMOS/PMOSTran.Depl.NMOS/PMOSTran.LVtNMOS/PMOSTransistor5VNMOS/PMOSTransistorFundamentalResistance0.5um5V/40VMixed-signalDeviceOptionsThanks