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国防科学技术大学硕士学位论文高速串行RapidIO下3.125GbpsCDR中相位插值器的设计姓名：邹黎申请学位级别：硕士专业：软件工程指导教师：彭元喜2011-04国防科学技术大学研究生院工程硕士学位论文第i页摘要在目前广泛应用的串行数据通信中，数据从发送端传输到接收端通常没有同步时钟的伴随。接收端接收到的数据极易受到偏斜和噪声的影响。为了恢复数据，需要一种电路能够提取时钟并且用它来同步和“清理”数据。这种电路即称为时钟数据恢复电路（CDR）。但是，接收端的数据往往在传输过程中积聚了抖动和噪声。为了准确地恢复数据并降低误码率，提取出来的时钟需要及时并精确地处理所接收到数据信号的相位。调整并恢复接收端数据的时钟相位是一个CDR电路的首要功能。相位插值器是时钟数据恢复电路中昀关键的模块。相位插值器的非线性会直接影响时钟数据恢复电路的动态特性，当输入数据与本地时钟存在频率差时，还会影响它的抖动容限。许多与高速信号传输有关的时序问题都是通过能够产生精确时钟相位的相位插值电路来解决的。本文在对RapidIO互联规范理解的基础上，根据CDR对相位插值器的性能要求，设计了一款应用于高速RapidIO下3.125GbpsCDR中的相位插值器，并使用0.13μmCMOS工艺实现。本文的主要工作以及创新之处包括以下几方面：1.研究和比较了CDR的几种常见实现结构，全面分析了电路的速度、抖动性和稳定性等设计要求，引入了基于锁相环结构的CDR。2.设计了一款高精度的相位插值器，该相位插值器的输出相位具有良好的单调性和线性，当CDR工作频率为3.125GHz/s时，该相位插值器的功耗小于9mw。3.由于相位插值器输出相位的幅度和线性度主要依赖于与两个输入相位之间的差距，这将导致输出相位的线性和单调性不够理想，本文引入了一种新的线性编码方式解决这个问题。4.遵循高速模拟电路版图设计规则，使用0.13μmCMOS工艺完成了相位插值器的版图设计，Hspice模拟结果显示该相位插值器达到工程设计要求。关键词：时钟数据恢复电路;相位插值器;相位选择;RapidIO国防科学技术大学研究生院工程硕士学位论文第ii页ABSTRACTInthewidelyusedserialcommunication,thedatawillbetransmittedfromtransmittertothereceiverwithoutasynchronousclock.Thereceiveddatasufferfromasynchronousandnoiseeffects.Torecoverthedata,thesystemneedstoextractaclockanduseittosynchronizeand“clear”thedata.Thissystemiscalledclockanddatarecovery(CDR).However,thereceiveddataaccumulatesjitterandnoiseduringtransmission.Torecoverthedatacorrectlyanddecreasethebiterrorrate(BER),theextractedclockneedstotrackthephaseofreceiveddatatimelyandaccurately.Thus,adjustingthephaseoftherecoveryclockbasedonthereceiveddataisachieffunctioninaCDRsystem.ThephaseinterpolatoristhemostcriticalmoduleinCDR.ThenonlinearityofphaseinterpolatorwilldirectlyaffectsthedynamiccharacteristicofCDR,evenleadstoerror.Whileafrequencydifferenceexistsbetweentheinputdataandthelocalclock,italsoaffectsthejittertoleranceofCDR.Manyofthetimingproblemsrelatedtohigh-speedsignallingaremitigatedthroughtheuseofphase-interpolatingcircuitstogeneratepreciseclockphases.ThepaperbasedontheinterpretationofRapidIOinterconnectarchitecture,withregardtotheperformancerequirementsofCDR,successfullyexploredacircuitofPIwiththe0.13umCMOStechnology,whichismainlyappliedtothe3.125GbpsCDRunderhigh-speedserialRapidIO.Themajorcontentsandhighlightsoftheresearchareasfollows:(1)ThroughthestudyandcomparisonofseveraldifferentkindsofCDR,andwithconsiderationofthemaximumdesignlimitsofspeed,jitterandstability,thepaperemployaCDRwhichbasedonPLLstructure.(2)Exploreahighprecisionphaseinterpolator.Testingresultsshowthatthephaseinterpolatorhasamonotoneoutputphaseandgoodlinearity.Thepowerdissipationofthephaseinterpolatorislessthan9mWwitha3.125GHz/sworkfrequency.(3)Theexperimentalresultshowsthattheoutputamplitudeandlinearityofphaseinterpolatorisprimarilyrelatedtothedifferencebetweenthetwoinputphases,whichresultsinthenonlinearityofthephaseinterpolator.Anewencodingpatternisgiventosolvethisproblem.(4)Withthehigh-speedanalogcircuitlayoutguidelines,completedthelayoutdesignwiththe0.13umCMOStechnology.TheHspicesimulationresultsshowthephaseinterpolatorweproposedwellmeetstheprojectdesignrequirement.KeyWords：CDR，phaseinterpolator，phaseselection，RapidIO国防科学技术大学研究生院工程硕士学位论文第IV页表目录表2.1互连技术比较....................................................................................................6表2.2物理层比较........................................................................................................8表2.3各种CDR结构优缺点比较............................................................................15表2.4RapidIO规范中的AC时钟规范–3.125GBaud.........................................20表2.5RapidIO规范中的眼图常量...........................................................................20表4.13-8译码逻辑....................................................................................................51表4.24-16译码逻辑..................................................................................................51表4.33-8译码逻辑验证结果....................................................................................56表4.44-16译码逻辑验证结果..................................................................................56表4.53-8译码逻辑二次验证结果............................................................................57表4.6相位选择表......................................................................................................59表4.7电路模拟三种条件..........................................................................................60表4.8相位插值表一..................................................................................................61表4.9相位插值表二..................................................................................................62表5.1相位插值器实现的特征参数..........................................................................74国防科学技术大学研究生院工程硕士学位论文第V页图目录图1.1串行链路结构示意图........................................................................................1图2.1RapidIO规范层次结构.....................................................................................7图2.2串行RapidIO物理层结构................................................................................9图2.3串行器/解串器...................................................