DDR布线权威参考设计

FreescaleSemiconductorApplicationNote©FreescaleSemiconductor,Inc.,2003,2006.Allrightsreserved.Embeddedsystemsthatusedoubledataratememory(DDR)canrealizeincreasedperformanceovertraditionalsingledatarate(SDR)memories.Asthenameimplies,DDRenablestwodatatransactionstooccurwithinasingleclockcyclewithoutdoublingtheappliedclockorwithouttodoublingthesizeofthedatabus.Thisincreaseddatabusperformanceisduetosource-synchronousdatastrobesthatpermitdatatobecapturedonboththefallingandrisingedgesofthestrobe.AlthoughDDRcanbringimprovedperformancetoanembeddeddesign,caremustbeobservedintheschematicandlayoutphasestoensurethatdesiredperformanceisrealized.Smallersetupandholdtimes,cleanerreferencevoltages,tightertracematching,newI/O(SSTL-2)signaling,andtheneedforproperterminationcanpresenttheboarddesignerwithanewsetofchallengesthatwerenotpresentforSDRdesigns.DocumentNumber:AN2582Rev.5,08/2006Contents1SSTL-2andTermination.......................22DDRSignalGroupings.........................43ControllerSignalPinout........................54BoardStack-Up...............................55LayoutOrderfortheDDRSignalGroups..........66LengthMatchingOverview.....................67LayoutGuidelinesfortheSignalGroups...........78LayoutGuidelinesforSpecificImplementations....229LogicAnalyzerSupportPackages...............2810InterfaceTimingAnalysisandOtherConsiderations2811ImprovingEyeDiagrams......................4112Simulation..................................4213DDRDesignerChecklist......................4314UsefulReferences............................4615RevisionHistory.............................46HardwareandLayoutDesignConsiderationsforDDRMemoryInterfacesbyDSDApplicationsFreescaleSemiconductor,Inc.Austin,TXHardwareandLayoutDesignConsiderationsforDDRMemoryInterfaces,Rev.52FreescaleSemiconductorSSTL-2andTerminationDesignchallengesconfrontingtheboarddesignercanbesummarizedasfollows:•Routingrequirements�Powersupplyanddecoupling,whichincludestheDDRdevicesandcontroller,theterminationrailgeneration(VTT),andreferencegeneration(VREF)�ProperterminationforagivenmemorytopologyThisapplicationnoteprovidesseverallayoutconsiderationswithintheseareasandincludesrecommendationsthatcanserveasaninitialbaselineforboarddesignersastheybeginspecificimplementation,whichcanconsistofthefollowing:�Singleormulti-DIMM—registered,unbuffered�SingleormultiSO-DIMM—registered,unbuffered�Soldered-downdiscreteimplementation�Mixture—discretesplusDIMMexpansionslotsBesidesmemory,compositememorytopologiescanalsoincludeon-boardlogicanalyzerconnectionsandexpansionDIMMcardswithanalyzerconnections.ThedesignguidelinesinthisdocumentapplytoPowerQUICC™productsthatleveragetheDDRIPcoreandarebasedonacompilationofinternalplatformsdesignedbyFreescale.Theseguidelinesminimizeboard-relatedissuesacrossmultiplememorytopologieswhileallowingmaximumflexibilityfortheboarddesigner.BecausenumerousmemorytopologiesandinterfacefrequenciesarepossibleontheDDRinterface,Freescalehighlyrecommendsthattheboarddesignerverify,throughsimulation,allaspects(signalintegrity,electricaltimings,andsoon)beforePCBfabrication.Also,besuretoconsultthelatesterrata.AnyACtimingparameterswithinthisdocumentareforreferencepurposesonly.ThedesignershouldconsulttheofficialACspecificationsforagivenproduct.1SSTL-2andTerminationForDDR-Imemories,JEDECcreatedandadoptedalowvoltage,high-speedsignalingstandardcalledseriesstubterminationlogic(SSTL).SSTLleveragesanactivemotherboardterminationschemeandovercomesthesignalintegrityconcernswithlegacyLVTTLsignaling.Asthenameimplies,SSTLissuitedforuseinmainstreammemoryinterfaceswherestubsandconnectorsarepresent.The2.5Vversion,namedSSTL-2,isprominentwithDDR1memoriesandisdefinedwithinJESD8-9B.Thememorycontrollersdriversandreceiversarecompatible.withSSTL-2.ThemostcommonSSTLterminationistheclassIIsingleandparallelterminationschemeshowninFigure1.Thisschemeinvolvesusingoneseriesresistor(RS)fromthecontrollertothememoryandoneterminationresistor(RT)attachedtotheterminationrail(VTT).ThisapproachisusedincommodityPCmotherboarddesigns.ValuesforRSandRTaresystem-dependentandshouldbederivedbyboardsimulation.SeeSection12,“Simulation,”foralistofpotentialterminationranges.UseofthemainstreamterminationincommodityPCmotherboardsisassumedinthisdocument.Consequently,differingterminationtechniquescanbevalidanduseful,butthedesignershouldusesimulationtovalidatethisdetermination.Inatypicalmemorytopology,theseriesdampingresistor(RS),ifused,isplacedawayfromthecontroller.Thisapproachhastwodistinctadvantages.Itfreespreciousboardspacearoundthememorycontroller,HardwareandLayoutDesignConsiderationsforDDRMemoryInterfaces,Rev.5FreescaleSemiconductor3SSTL-2andTerminationavoidinglayoutcongestionandburdensomefanout.Also,itoptimizesthesignalintegrityforthesignalssentfromthecontrollertothememories,wheremoresignals(addr+cmd)mustbereliablyreceivedbymultipledevices.Figure1.TypicalMemoryInterfaceUsingClassIIOptionTorealizetheincreasedsignalingfrequencies,SSTLleverageshigh-gaindifferentialreceiversthatarebiasedaroundareferencevoltagedenotedasVREF.Usingt