搜索
21120093()JOURNALOFHENANINSTITUTEOFENGINEERINGVol121,No11Mar.2009VHDL1,2,2(1.,710048;2.,451191):,VHDL,,PLD..:;;;VHDL:TN79:A:1674-330X(2009)01-0058-05:2008-10-21:(1967-),,,,.,,,,,.VHDL,VHDL.1434[1],1.,keyin0keyin310K103.1434Fig.1Thewholeblockdiagramof434eliminatebounceandmatrixkeyboard2D[2-4].,2,RS©1994-2010ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.:VHDL,[4].2Fig.2TheblockdiagramofsamplingandeliminatebouncedifferentiatorVHDL.entityfd_rsisport(clk_fd,keyin:instd_logic;--qr:bufferstd_logic;--:qrkeyout:outstd_logic);end;architectureaoffd_rsissignalr,s,qs,d1,d2,q2,d3,d4,q4,cp:std_logic;signalqr:std_logic;--:beginprocess(clk_fd)beginif(clk_fd’eventandclk_fd=’1’)thend1=notkeyin;--d2=d1;q2=d2;d3=qr;d4=d3;q4=d4;endif;r=(notd2)and(notq2);s=d2andq2;--qr=rnorqs;qs=snorqr;--RScp=d4and(notq4);keyout=notcp;--endprocess;--outputend;,10ms(),6ms,,.QuartusII7.03.,keyin,qr,keyout,.3Fig.3Simulationwaveformofsamplingandeliminatebouncedifferentiator95©1994-2010ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.()20093(keydrv3keydrv0),(keyin3keyin0).,.,;,.keydrv3keydrv0,keyout3keyout01.1Tab.1TherelationofrowscanningsignalcolumnkeyeliminatebounceincomingsignalandkeymarkKeydrv3keydrv0Keyout3keyout0Keydrv3keydrv0Keyout3keyout011101110111011100101111101011111081101111011011110110111101910111110101121011101110111001111110011130111101101111111011110110111104011111100111111012110111011101511010111110113101111011011610110111101114011111010111701110111011115keydrv3keydrv0keyout3keyout0,1.keypressed.,.4.,clk,PLD.clk,.Key_drv,key_out,keyvalue(),key_pressed,,key_pressed.,.key_pressed,.functionkey(101112131415).,functionkey,.,VHDL.4keydrv3keydrv0,1110110110110111.4KEYSAN.clk_scan10ms,key_drv,4.,VHDL.,,4CLKGEN.,12MHz.10ms.,VHDL.,,.06©1994-2010ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.:VHDL5,4,VHDL.CLK2GEN,FD_RS,KEYSCAN,KEYDECODER.key_out[3..0],.QuartusII7.05.key_drv=1101key_in=1110,keyvalue0100(4);key_drv=1110key_in=1110,keyvalue0000(0);key_drv=0111key_in=1110,keyvalue1100(12)1,.6VHDL,VHDLQuartusII7.0EDA,,,.16©1994-2010ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.()2009:[1].CPLD/FPGA[M].:,2005.359-371.[2],.[J].(),2003,(6):42-44.[3],.FPGA[J].,2006,(3):53-55.[4],.EDA-VHDL[M].:,2003.92-97.[5].VHDL[M].:,2005.115-121.DesignofEliminateBounceandMatrixKeyboardBasedonVHDLLUChuanming1,2,WONGJiamin2(1.Xi’anPolytechnicUniversity,Xi’an710048,China;2.HenanInstituteofEngineering,Zhengzhou451191,China)Abstract:Thisresearchintroducedthewholedesignthoughtofeliminatingbounceandmatrixkeyboard.Andthen,itadoptedmodulardesigntechniqueanddesignedeachcircuitbasedonVHDLprogramming.Atlast,thestudyproceedsdesignandsimulationoftopdocumentandprogrammedcertificatewithPLDdevice.Thewholecircuithadthefeaturesoflowerfaultrate,goodflexibility,beingeasilymodified,insystemprogrammabilityandpowerfultransplantablecapability.Keywords:modularizationdesign;keyboard;eliminatebounce;VHDL26©1994-2010ChinaAcademicJournalElectronicPublishingHouse.Allrightsreserved.