NXP Keil LPC1768 ARM Cortex-M3 MCU开发方案

NXP公司的LPC1769/68/67/66/65/64/63是基于ARMCortex－M3核的微控制器,具有高度集成和低功耗,工作频率高达100MHz/120MHz,采用三级流水线和哈佛架构,具有独立的本地指令,数据总线和用于外设的第三总线,高达512KB闪存,主要用在电表,告警系统,照明系统,白色家电,工业网络和马达控制.本文介绍了LPC1769/68/67/66/65/64/63主要特性和优势,框图,以及KeilLPC1768评估板MCB1700主要特性和电路图.AlpsElectricAnalogDevicesIR(InternationalRectifier)JRC/NJRKECOTAXRFMDSamsungElectro-MechanicsSeoulSemiconductorTI(TexasInstruments)WalsinTechnologyTheLPC1769/68/67/66/65/64/63areARMCortex-M3basedmicrocontrollersforembeddedapplicationsfeaturingahighlevelofintegrationandlowpowerconsumption.TheARMCortex-M3isanextgenerationcorethatofferssystemenhancementssuchasenhanceddebugfeaturesandahigherlevelofsupportblockintegration.TheLPC1768/67/66/65/64/63operateatCPUfrequenciesofupto100MHz.TheLPC1769operatesatCPUfrequenciesofupto120MHz.TheARMCortex-M3CPUincorporatesa3-stagepipelineandusesaHarvardarchitecturewithseparatelocalinstructionanddatabusesaswellasathirdbusforperipherals.TheARMCortex-M3CPUalsoincludesaninternalprefetchunitthatsupportsspeculativebranching.傲壹电子—电子元器件分销商官网：中文网：(RTC)withseparatebatterysupply,andupto70generalpurposeI/Opins.TheLPC1769/68/67/66/65/64/63arepin-compatibletothe100-pinLPC236xARM7-basedmicrocontrollerseries.LPC1769/68/67/66/65/64/63主要特性和优势:ARMCortex-M3processor,runningatfrequenciesofupto100MHz(LPC1768/67/66/65/64/63)orofupto120MHz(LPC1769).AMemoryProtectionUnit(MPU)supportingeightregionsisincluded.ARMCortex-M3built-inNestedVectoredInterruptController(NVIC).Upto512kBon-chipflashprogrammingmemory.Enhancedflashmemoryacceleratorenableshigh-speed120MHzoperationwithzerowaitstates.In-SystemProgramming(ISP)andIn-ApplicationProgramming(IAP)viaon-chipbootloadersoftware.On-chipSRAMincludes:32/16kBofSRAMontheCPUwithlocalcode/databusforhigh-performanceCPUaccess.Two/one16kBSRAMblockswithseparateaccesspathsforhigherthroughput.TheseSRAMblocksmaybeusedforEthernet,USB,andDMAmemory,aswellasforgeneralpurposeCPUinstructionanddatastorage.EightchannelGeneralPurposeDMAcontroller(GPDMA)ontheAHBmultilayermatrixthatcanbeusedwithSSP,I2S-bus,UART,Analog-to-DigitalandDigital-to-Analogconverterperipherals,timermatchsignals,andformemory-to-memorytransfers.MultilayerAHBmatrixinterconnectprovidesaseparatebusforeachAHBmaster.AHBmastersincludetheCPU,GeneralPurposeDMAcontroller,EthernetMAC,andtheUSBinterface.Thisinterconnectprovidescommunicationwithnoarbitrationdelays.SplitAPBbusallowshighthroughputwithfewstallsbetweentheCPUandDMA.Serialinterfaces:EthernetMACwithRMIIinterfaceanddedicatedDMAcontrollerUSB2.0full-speeddevice/Host/OTGcontrollerwithdedicatedDMAcontrollerandon-chipPHYfordevice,Host,andOTGfunctions.FourUARTswithfractionalbaudrategeneration,internalFIFO,andDMAsupport.OneUARThasmodemcontrolI/OandRS-485/EIA-485support,andoneUARThasIrDAsupport.CAN2.0Bcontrollerwithtwochannels.SPIcontrollerwithsynchronous,serial,fullduplexcommunicationandprogrammabledatalength.TwoSSPcontrollerswithFIFOandmulti-protocolcapabilities.TheSSPinterfacescanbeusedwiththeGPDMAcontroller.ThreeenhancedI2Cbusinterfaces,onewithanopen-drainoutputsupportingfullI2CspecificationandFastmodepluswithdataratesof1Mbit/s,twowithstandardportpins.Enhancementsincludemultipleaddressrecognitionandmonitormode.I2S(Inter-ICSound)interfacefordigitalaudioinputoroutput,withfractionalratecontrol.TheI2S-businterfacecanbeusedwiththeGPDMA.TheI2S-businterfacesupports3-wireand4-wiredatatransmitandreceiveaswellasmasterclockinput/output.Otherperipherals:70(100pinpackage)GeneralPurposeI/O(GPIO)pinswithconfigurablepull-up/downresistors.AllGPIOssupportanew,configurableopen-drainoperatingmode.TheGPIOblockisaccessedthroughtheAHBmultilayerbusforfastaccessandlocatedinmemorysuchthatitsupportsCortex-M3bitbandingandusebytheGeneralPurposeDMAController.12-bitAnalog-to-DigitalConverter(ADC)withinputmultiplexingamongeightpins,conversionratesupto200kHz,andmultipleresultregisters.The12-bitADCcanbeusedwiththeGPDMAcontroller.10-bitDigital-to-AnalogConverter(DAC)withdedicatedconversiontimerandDMAsupport.Fourgeneralpurposetimers/counters,withatotalofeightcaptureinputsandtencompareoutputs.Eachtimerblockhasanexternalcountinput.SpecifictimereventscanbeselectedtogenerateDMArequests.OnemotorcontrolPWMwithsupportforthree-phasemotorcontrolQuadratureencoderinterfacethatcanmonitoroneexternalquadratureencoder.OnestandardPWM/timerblockwithexternalcountinput.RTCwithaseparatepowerdomainanddedicatedRTCoscillator.TheRTCblockincludes20bytesofbattery-poweredbackupregisters.WatchDogTimer(WDT).TheWDTcanbeclockedfromtheinternalRCoscillator,theRTCoscillator,ortheAPBclock.ARMCortex-M3systemti