Cavium_OCTEON培训资料

CaviumNetworksConfidentialPage1OCTEONTechnicalPresentationCaviumNetworksConfidentialPage2Agenda●LessonOneOcteonArchitectureIntroduceOcteon报文处理流程●LessonTwoFPATimer●LessonThreePIP/IPDPKO●LessonFourSSO●LessonFiveSoftwareoverviewCaviumNetworksConfidentialPage33OCTEON多核处理器架构介绍CaviumNetworksConfidentialPage42MBSharedL2CacheHyperAccessMemoryControllerHyperAccessMemoryControllerCoherent,Low-latencyInterconnectHyperAccessLowLatencyMemoryControllerHyperAccessLowLatencyMemoryControllerOptional2x18-bitRLDRAM2DDR2upto800MHz72or144-bitwideSPI4.2or4xRGMIISPI4.2or4xRGMIIBoot/flashGPIO2xUART64-bit,133MHzCompress/DecompCompress/Decomp32xRegExEngines32xRegExEnginesPacketInterfacePacketInterfacePacketInterfacePacketInterfaceMiscI/OMiscI/OSecureVaultSecureVaultPCI-XPCI-XTCPUnitTCPUnitI/OBusSched/Synch/OrderSched/Synch/OrderUpto16cnMIPS+coresSecurityMIPS64r2IntegerPacket32KIcache16KDcache2KWriteBufferSecurityMIPS64r2IntegerPacket32KIcache16KDcache2KWriteBufferPacketInputPacketInputPacketOutputPacketOutputI/OBridgeI/OBridge640Gbps136GbpsOCTEONPlusCN58XXCaviumNetworksConfidentialPage5Low-latencyInterconnectDDR2-8001xor2x72bitwide(withECC)Boot/flash,GPIO,MISC,USB2.0,FEI/OBusSched/Synch/OrderSched/Synch/Order8-12cnMIPS+CoresSecurityMIPS64r2IntegerPacket32KIcache16KDcache2KWriteBufferPacketInputPacketInputI/OBridgeI/OBridge2MBL2CacheHyperAccessMemoryControllerSecurityMIPS64r2IntegerPacket32KIcache16KDcache2KWriteBufferPacketOutputPacketOutputTCPUnitTCPUnitCompression+DecompressionCompression+Decompression4xPCIeCorePCIeCore4xSGMIIor4x1000B-XorXAUI4x4x4xSwitchPCIeEngines4xSGMIIor4x1000B-XorXAUIOtherI/OOtherI/Ox16SerdesenablescombinationofPCIe(2controllers),XAUI,SGMIIanduptodoublespeedPICMGinterfaceswithPCIeswitching*DMAEnginesDMAEngines*InterfaceOptions*InterfaceOptions●8-lanesPCIe+8-lanesPCIe8-lanesPCIe+8-lanesPCIe●8-lanesPCIe+4-lanesPCIe+[4xSGMIIorXAUI]8-lanesPCIe+4-lanesPCIe+[4xSGMIIorXAUI]●2x[4-lanesPCIe]+2x[4xSGMIIorXAUI]2x[4-lanesPCIe]+2x[4xSGMIIorXAUI]RAIDRAIDOCTEONPlusCN56/57XXCaviumNetworksConfidentialPage6Low-latencyInterconnectDDR2-8001xor2x72bitwide(withECC)Boot/flash,GPIO,MISC,USB2.0,FEI/OBusSched/Synch/OrderSched/Synch/Order4-6cnMIPS+CoresSecurityMIPS64r2IntegerPacket32KIcache16KDcache2KWriteBufferPacketInputPacketInputI/OBridgeI/OBridge1MBL2CacheHyperAccessMemoryControllerSecurityMIPS64r2IntegerPacket32KIcache16KDcache2KWriteBufferPacketOutputPacketOutputTCPUnitTCPUnitCompression+DecompressionCompression+Decompression4xPCIeCorePCIeCore4x4x4xSwitchPCIeEngines4xSGMIIor4x1000B-XorXAUIOtherI/OOtherI/Ox16SerdesenablescombinationofPCIe(2controllers),XAUI,SGMIIanduptodoublespeedPICMGinterfaceswithPCIeswitching*DMAEnginesDMAEngines*InterfaceOptions*InterfaceOptions●8-lanesPCIe+4-LanesPCIe+[4xSGMIIorXAUI]8-lanesPCIe+4-LanesPCIe+[4xSGMIIorXAUI]●8-lanesPCIe+8-LanesPCIe8-lanesPCIe+8-LanesPCIeRAIDRAIDOCTEONPlusCN54/55XXCaviumNetworksConfidentialPage7LowLatencyCoherentInterconnect800-DDR272bitwide(withECC)4xSGMIIorTCPUnitTCPUnitI/OBusSched/Synch/OrderSched/Synch/Order2-4cnMIPS+CoreSecurityMIPS64r2IntegerPacket32KIcache16KDcache2KWriteBufferPacketInputPacketInputPacketOutputPacketOutputI/OBridgeI/OBridge512KBL2CacheHyperAccessMemoryControllerSecurityMIPS64r2IntegerPacket32KIcache16KDcache2KWriteBuffer4x4x4x4xPCIePCIeMIIMIINOR,CompactFlashBoot/flash,GPIO,3xUARTs2xMIIUSB2.0USB2.02xUSB2.0PHY1x4PCIeor2x2PCIeMiscI/OMiscI/ODMAEnginesDMAEngines1x10GESGMII/XAUISGMII/XAUIOCTEONPlusCN52XXCaviumNetworksConfidentialPage8128KBSharedL2CacheHyperAccessMemoryControllerHyperAccessMemoryControllerCoherentBusDDR232/36bitwideI/OBusSched/Synch/OrderSched/Synch/Order1-2cnMIPS+coresSecurityMIPS64r2IntegerPacket32KIcache16KDcache2KWriteBufferPacketInputPacketInputPacketOutputPacketOutputI/OBridgeI/OBridgeBoot/flashGPIO2xUART32-bit,66MHzPacketInterfacePacketInterfaceMiscI/OMiscI/ORNGRNGPCIPCITCPUnitTCPUnit3xRGMIIUSBUSBUSB2.0Hostw/PHYTDM/PCMTDM/PCMTDM/PCMSecurityMIPS64r2IntegerPacket32KIcache16KDcache2KWriteBufferOCTEONPlusCN50XXCaviumNetworksConfidentialPage94x72bDDR31600DDR32GBmaxFPASched/Synch/Orderv2PacketInputv2PacketOutputv2I/OBridgeRAIDDMALowLatencyInterconnectUpto32cnMIPSIIcoresSecurityMIPS64r2IntegerPacket38KIcache32KDcache2KWriteBufferTimersBootFlash,GPIO,USB2,2xUART,MIIMiscI/OSecurityMIPS64r2IntegerPacket38KIcache32KDcache2KWriteBuffer4MBSharedL2Cache4xHyperAccessMemoryControllerv24x16bDDR3or80bitTCAMIORegularExpressionMemoryControllerGrammarProcessorSecVaultx20Gen2Serdesx5Gen2SerdesLook-upAssistDe/Comprsx4x4x4x4x4XAUIor4xSGMIIXAUIor4xSGMIIXAUIor4xSGMIIXAUIor4xSGMIIPCIev2PCIev2x5Interlaken3-4xApplicationPerformanceoverOCTEONPlusUpto60MPPSIPForwardingUpto48+GHzofcomputecycles100+GbpsofNetworkIOconnectivityOCTEONIICN68XXPreliminaryBlockDiagramCaviumNetworksConfidentialPage10OCTEONMulti-CoreMIPS64ProcessorFamily●StandardMIPS64ISAStandardOS’s(Linux,VxWorks,etc)StandardCBasedsoftware●MultiCoreArchitectureIntegrates1coreto16coresonasinglechip●Integratedper-coreHWaccelerationenginesfordata,contentandsecurity●Integratedco-processorsTCP,IDS,An