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江苏科技大学本科毕业设计（论文）学院专业学生姓名班级学号指导教师二零壹叁年六月江苏科技大学本科毕业论文基于FPGA的异步FIFO设计AsynchronousFIFOdesignbasedonFPGA江苏科技大学本科毕业设计（论文）I摘要在现代集成电路芯片中，随着设计规模的不断扩大，一个系统往往包含多个时钟，如何进行异步时钟间的数据传输成为了一个很重要的问题。异步FIFO（FirstInFirstOut）是一种先进先出电路，可以在两个不同的时钟系统间进行快速准确的数据传输，是解决异步时钟数据传输问题的简单有效的方案。异步FIFO在网络接口、数据采集和图像处理等方面得到了十分广泛的应用，由于国内对该方面研究起步较晚，国内的一些研究所和厂商开发的FIFO电路还远不能满足市场和军事需求。由于在异步电路中，时钟间的周期和相位完全独立，以及亚稳态问题的存在，数据传输时的丢失率不为零，如何实现异步信号同步化和降低亚稳态概率以及正确判断FIFO的储存状态成为了设计异步FIFO电路的难点。本课题介绍了一种基于FPGA的异步FIFO电路设计方法。课题选用QuartusII软件，在CycloneII系列的EP2C5T144C8N芯片的基础上，利用VHDL硬件描述语言进行逻辑描述，采用层次化、描述语言和图形输入相结合的方法设计了一个RAM深度为128bit，数据宽度为8bit的高速、高可靠的异步FIFO电路，并对该电路功能进行时序仿真测试和硬件仿真测试。关键词：异步FIFO；同步化；亚稳态；仿真测试江苏科技大学本科毕业设计（论文）IIAbstractInmodernICchips,withthecontinuousexpansionofthescaleofdesign,asystemalwayscontainsseveralclocks.Howtotransmitdatabetweentheasynchronousclocksbecomeaveryimportantproblem.AsynchronousFIFO(FirstInFirstOut)isafirst-in,first-outcircuit,itcantransmitdatabetweentwodiffentclocksystemsfastlyandaccurately,itisalsoasimpleandeffectivesolutiontosolvetheproblemofasynchronousclockdatatransfer.TheasynchronousFIFOhasaverywiderangeofapplicationsinnetworkinterface,dataacquisitionandimageprocessing.Butbecauseoftheaspectofalatestart,somedomesticresearchinstitutesandmanufacturerswhichresearchtheFIFOcircuitalsocannotmeettheneedsofthemarketandthemilitary.Intheasynchronouscircuit,becauseofthattheclockcycleandphaseiscompletelyindependent,andthepresenceofmetastabilityproblems,thelossrateofdatatransmissionisnotzero.Howtoimplementasynchronoussignalsynchronization,reducetheprobabilityofmetastabilityandjudgethestateoftheFIFOstoragecorrectlybecomeadifficultproblemwhiledesigningtheasynchronousFIFOcircuit.ThispaperintroducesamethodofasynchronousFIFOcircuitdesignbasedonFPGA.ThistopicselectsQuartusIIsoftware,theCycloneIIfamilyEP2C5T144C8Nchip,basedontheuseofVHDLhardwaredescriptionlanguageforlogicaldescriptions,usingthemethodofcombininghierarchical,descriptionlanguageandgraphicalinput,Thistopicdesignsahigh-speed,highlyreliableasynchronousFIFOcircuitastheRAMdepthis128bitandthedatawidthis8bit,andteststhecircuitfunctionwithtimingandsoftwaresimulation.Keywords:AsynchronousFIFO;Synchronization;Metastability;simulationtesting江苏科技大学本科毕业设计（论文）III目录第一章绪论......................................................11.1FPGA简介.....................................................11.2异步FIFO简介.................................................11.3国内外研究现状及存在的问题....................................11.3.1研究现状..................................................11.3.2存在问题..................................................21.4本课题主要研究内容............................................3第二章异步FIFO设计要求及基本原理........................42.1设计要求......................................................42.2异步FIFO基本原理.............................................52.3异步FIFO设计难点.............................................52.4系统设计方案..................................................62.5异步FIFO验证方案.............................................72.5.1验证复位功能..............................................72.5.2验证写操作功能............................................72.5.3验证读操作功能............................................72.5.4验证异步FIFO电路整体功能.................................7第三章模块设计与实现.........................................83.1格雷码计数器模块..............................................83.2同步模块......................................................83.3格雷码∕自然码转换模块........................................93.4空满标志产生模块.............................................103.5双端口RAM...................................................13第四章时序仿真与实现........................................154.1模块整合.....................................................15江苏科技大学本科毕业设计（论文）IV4.2时序仿真及功能测试...........................................174.2.1复位功能软件仿真与测试...................................174.2.2写操作功能时序仿真与测试.................................174.2.3读操作功能时序仿真与测试.................................184.2.4异步FIFO电路整体功能软件仿真与测试......................184.2.5时序仿真结果总结.........................................19第五章硬件仿真与实现........................................205.1外部电路焊接.................................................205.2引脚分配.....................................................215.3调试电路设计.................................................245.3.1调试电路介绍.............................................245.3.2异步时钟产生模块.........................................255.3.3伪随机数据队列产生模块...................................255.3.5调试电路引脚分配.........................................265.3.6调试电路硬件仿真.........................................275.4异步FIFO电路硬件仿真........................................285.4.1复位功能硬件仿真与测试...................................295.4.2写操作功能硬件仿真与测试.................................305.4.3读操作功能硬件仿真与测试.................................305.4.4异步FIFO硬件电路整体功能软硬件仿真与测试................315.4.5硬件仿真结果总结.........................................32结论.............................................................33致谢.............................................................34参考文献........................................................3