基于FPGA的心电信号处理研究与实现

广西师范大学硕士学位论文基于FPGA的心电信号处理研究与实现姓名：杨秀增申请学位级别：硕士专业：电路与系统指导教师：黄秉錬20070401IFPGA20041906FPGAFPGADSPMCUCPUFPGAAD62050HzFPGAFPGAFPGAFIRFPGAFPGAA/DADC0809FPGAFIRFPGAFPGAFIRSOPCIITheStudyandRealizationofECGSignalProcessingonFPGAspecialty:ciruitsandsystemsresearchdirection:computercontrolandexaminationtechnologyAdvisers:prof.HUANGBing-lianGraduatestudent:YANGXiuzeng(Grade2,004)AbstractElectrocardiogram(ECG)isabioelectricsignalproducedbymyocardialcontractilityandcanshowthechangesofphysiologicalactioninheart.Itfindsbroadapplicationinclinicalmedicinebecauseitiseasytocheckonandcanisdirectlyperceived.In1906,thefirstECGmachinewasusedinclinicalmedicine,sincethat,allkindsofECGmonitorinstrumentsemergedinanendlessstream.Atpresent,thekeytodesignanddevelopthemulti-functionalECGmonitorproductsstilldependsontheadvancedtechniquesandwaystoprocesstheElectrocardiogram.Thesubjectfortheauthor’sstudyistoapplyFPGAtechniquestodeveloptheElectrocardiogrammachine.Thatistosaythatthe“chiponsystem”ofFPGAreplacesthecomplexsystemofDSPandtheCPU,whichwasusedinexistingECGmonitorinstrumentsandthusdevelopanECGmonitorinstrumentbasedonFPGAtocollect,process,review,memoryandcommunicateandshowsignals.InordertobuildatestplatformforprocessingtheECGsignal,thetopichasfirstlydesignedapre-amplificcircuit.whichmainlyconsistsoftheAD620amplifyingcircuit.,bandpassFilterCircuit,50Hznotchfilter,rightfloatinggrounddriveringcircuit,principalmagnifyingcircuitandpotentialraisingcircuit.ItismainlytocollectavailablesignalsfromtheheartandenhancethesignaltonoiserateandthenapplyFPGAtechniquestoacquireandprocessthesignals,whichincludesthreefunctionssuchasdataacquisitionsystemcontrolledbyFPGA,FIRlowpassfilter,andFPGAadaptivefilter.TheroleofdataacquisitionsystemaretoacquiresignalsbyapplyingA/DchipADC0809thatiscontrolledbyFPGAandmaketransitionanaloguesignalsintodigitalsignals.FIRlowpassfilterofFPGA,andFPGAadaptivefilterareusedtoprocessdataandthusgetdesirableelectrocardiogram.KeyWords:electrocardiogramFPGAdataacquisitionsystemFIRfilter2131906DSPMCUDSP90nmFPGAFPGAFPGADSPMCUCPUAvalonAvalon32NiosIICPU6-1NiosIICPUFPGA2EDA90nm1985XilinxFPGAFPGAFPGA12002CPUDSPSOPC131311AD62050Hz2FPGA3FPGA89FIR4FPGA532NiosIISOPC132FPGAFPGAFIRFPGA3(electrocardiogramECG)AD62021[1]PQRSTUP-RS-TQ-T2-1P0.10.35mVPPQRS0.01TT0.5~0.25TQRSP-R0.12-0.2042-1P-RSTQRSTP:()()Q-TQRST()0.39±0.0422[2]2-2ab2-25Us104RT1,RT2Rs1,Rs2E1,E2Cs1,Cs2C1,C21;RL1,RL2;Ri23231[3]50Hza12-3I2-3C1C2Z16Z2ZgId1,Id2Z1Z22-3(b)Z1=Z2C1=C2Id1=Id2=6nA,Z1,Z25kΩUAB=Id1(Z1-Z2)=30µV3%b2-4Id=0.2µA.0.2µA400Ω2=160µV16%2-4c50Hz2-5Bcosθ3.210-7Wb/m20.1m210µV7232---2-52332Hzl0kHz502-62-6234ECGECGECG5Hz2-72-78235242-850HZAD620AD6201050HZ50HZA/DA/D2-8241AD620AD620AnalogDevices1l0G21100031CMRR73dB410CMRR93dB5100CMRR110dB6125µV1µV/00C70.1Hzl0Hz0.28µVp-pAD6202-9AD620C1C2R1R2AD620U2U350HZ92-9AD62024250HZ50HZ50HZAD62050HZ50HZ2-102-10QT10QC1C2C3R1R2R3TU2R4R5QR4R5Q221()()12(2)()vsCRAsAsCRsCR+=+−+2-1455vRRAR+=0fRC012fRCπ=2-2[4]11121301231312CCfCCCRRπ+=2-321232100gRRRR==≥2-432132CCC==2-54112233RCRCRC==2-6Rg2CR2430.05Hz~100Hz2-11U1U2U1R1=R2=R=68k,C1=C2=C=47uF1Ao=AVF=12-72221()11211(3)()1()VFVFAASAsRCsRCsRCsRC==+−+++2-8112-11336110.0522*3.14*68*10*47*10lfHzRCπ−==≈2-941132VFQA==−2-10U2R3=R4=R=1.6k,C3=C4=C=1uF1Ao=AVF=12-112221()1(3)()12()VFVFAASAsRCsRCsRCsRC==+−+++2-12123361110022*3.14*1.6*10*1*10hfHzRCπ−==≈2-13244A/DA/DA/DADC08090~5V2-12U12-12R5R62452-1003Hz~98Hz50Hz496Hz50Hz105Hz50Hz45dB800CMRR69dB2-1132-132-1314FPGAA/DFPGAFPGA31[5]T3-1xa(t)$xa(t)xa(t)0Ta(b)p(t)=T(t)$xa(t)0T0T(c)(d)3.-11532A/D3-2(j)=001,||/20,||/2ΩΩΩΩ3-143-2A/D,,3-3CS(j)cs3-3|(j)|dBADC(Amin)CO2TO3-43-40=2πTA/D16H(j)H(j)ADCmin=20log(1.52×B)A/DBADC3-4OcADC3-1ADCmin=20log(1.52×B)minADCBmin(dB)8501062127416983-1ADCBADCA/D3-5x(n)xd(n)3-5D1733FPGAADC0809FPGAADC0809331A/DADC08093-6ADC08098256SAR3-7ADC0809STARTADC0809SARADC0809ALEADDAADDBADDCEOCADC0809ADC0809OESTARTCLOCKIN026EOCIN127IN228212-11202-2IN42192-3IN5312-4IN6482-5IN75152-6ADDA12-7ADDB172-8ADDCOEALE12153-6ADC080925618CLOCKSTART||||ALE||||EOC||||||OEOUTPUT-----------------------------------------------------3-7ADC08093323-8ADC0809FPGA50500ADC08095ADC080925MHZ500KHZSTART1KHZALEenansresetSreqFPGAEOCOEhold3-8ADC080950500ADC0809195025MHz50500KHzADC0809500ADC0809500500KHz5001KHzADC0809STARTALE1KHzADC0809ADC0809ADC08095ADC0809333ADC08093-9ADC0809ADC0809FPGAFPGA3-10OEholdSTARThold=1A/DADC0809A/DEOCOEADC080920NYESN3-9ADC0809START=1EOC=13-10ADC0809START=1A/DEOC=1A/D213343-8enreqans,req3-11FPGANYESNYES3-11FPGA3-12FPGAEnReqAnwReq22335VerilogHDLVerilogHDLQuartusIIFPGA3-123-133-143-133-1423FPGAFIR100HzFIRIIRFIRh(n)IIRh(n)4-14-2Hz=10Nk−=∑h(k)z--k(4-1)Hz=0Nk=∑bkzk/(1+0Nk=∑akz–k)(4-2)IIRIIRFIRFIR41FIR[6]FIR411(4-1)y(n)=10Nk−=∑h(k)x(n-k)(4-3)NFIRy(n)h(k)k=02412Nx(n)4-1FIR4-1FIR4-24-1FIR4-2FIR4124-1Hz=10Nk−=∑h(k)z–k=/21Nk=∏0K+1KZ-1+2KZ–24-4NFIR4-3X(n)01020[N/2]--------Z–1Z–1Z-111121[N/2]Z–2Z–2Z–221222[N/2]254-3FIRN413FIRFFT4-4x(n)X(k)⊗h(n)H(K)y(n)4-4FIR414FIRFIRMM4-54-64-5FIRFFTIFFTh(n)FFTIFFT264-6FIR42FIR[7]FIR54-7()matlabH(z)()274-7FIR43FPGAFIRFPGAFPGAFPGAFPGAFPGA