(内存基本知识)-DRAM工作原理

RamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAM工作原理DRAM工作原理RamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidential•DynamicRandomAccessMemory•Eachcellisacapacitor+atransistor–Verysmallsize–SRAMusessixtransistorspercell•Dividedintobanks,rows&columns–EachbankcanbeindependentlycontrolledDRAMRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialMainMemoryEverythingthathappensinthecomputerisresidentinmainmemoryCapacity:around100Mbyteto100GbyteRandomaccessTypicalaccesstimeis10-100nanosecondsWhyDRAMforMainMemory??􀂄Costeffective(smallchipareathanSRAM)􀂄HighSpeed(thanHDD,flash)􀂄HighDensity(~Gbyte)􀂄MassProduction……MainmemoryRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialNotation:K,M,G􀂄Instandardscientificnomenclature,themetricmodifiersK,M,andGtorefertofactorsof1,000,1,000,000and1,000,000,000respectively.􀂄ComputerengineershaveadoptedKasthesymbolforafactorof1,024(210)􀂄K:1,024(210)􀂄M:1,048,576(220)􀂄G:1,073,741,824(230)􀂄DRAM’density􀂄256M-bit􀂄512M-bitRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAMDensityRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialWhatisaDRAM?•􀂄DRAMstandsforDynamicRandomAccessMemory.•􀂄RandomaccessreferstotheabilitytoaccessanyoftheinformationwithintheDRAMinrandomorder.•􀂄Dynamicreferstotemporaryortransientdatastorage.Datastoredindynamicmemoriesnaturallydecaysovertime.Therefore,DRAMneedperiodicrefreshoperationtopreventdataloss.RamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialMemory:DRAMposition􀂄Semiconductormemorydevice􀂄ROM:Nonvolatile􀂄MaskROM􀂄EPROM􀂄EEPROM􀂄Flash􀂄NAND:lowspeed,highdensity􀂄NOR:highspeed,lowdensity􀂄RAM:Volatile􀂄DRAM:DynamicRandomAccessMemory􀂄SRAM:StaticRandomAccessMemory􀂄PseudoSRAMRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAMTrend:Future􀂄HighSpeed-DDR(333MHz~500MHz),DDR2(533~800Mbps),DDR3(800~1600Mbps)-Skew-delayminimizedcircuit/logic:post-chargelogic,wave-pipelining-NewArchitecture:multi-bankstructure,highspeedInterface􀂄LowPower-5.5V=3.3V(sdr)=2.5V(ddr)=1.8V(ddr2)=1.5v(ddr3)=1.2v?-SmallvoltageswingI/Ointerface:LVTTLtoSSTL,opendrain-LowPowerDRAM(PASR,TCSR,DPD)􀂄HighDensity-Memorydensity:32MB=64MB=.....1GB=2GB=4GB-applicationexpansion:mobile,memoryDBforshock(thanHDD)-Processshrink:145nm(‘03)=120nm(‘04)=100nm=90nm=80nm…􀂄OtherTrends-CostEffectiveness,TechnicalCompatibility,Stability,Environment.ReliabilityRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialStaticRAM•SRAM–Basicstorageelementisa4or6transistorcircuitwhichwillholda1or0aslongasthesystemcontinuestoreceivepower–Noneedforaperiodicrefreshingsignaloraclock–Usedinsystemcache–Fastestmemory,butexpensiveSRAMElementEnableLine/BitLineBitLineRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDynamicRAM•DRAM–Densertypeofmemory–Madeupofone-transistor(1-T)memorycellwhichconsistsofasingleaccesstransistorandacapacitor–CheaperthanSRAM–Usedinmainmemory–MorecomplicatedaddressingschemeDRAMCellWordLineBitLineRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialRefreshinDRAMsCapacitorleaksovertime,theDRAMmustbe“REFRESHED”.DRAMCellWordLineBitLineCapacitanceLeakageRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialSRAMvs.DRAMRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAMLeadFrameandWirebondingRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAMArchitectureRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidential–SDRAMhasthemultibankarchitecture.–ConventionalDRAMwasproductthathavesinglebankarchitecture.–Thebankisindependentactive.memoryarrayhaveindependentinternaldatabusthathavesamewidthasexternaldatabus.–Everybankcanbeactivatingwithinterleavingmanner.–Anotherbankcanbeactivatedwhile1stbankbeingaccessed.(Burstreadorwrite)MultiBankArchitectureRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAMMultiBankArchitectureRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAMSingleBankArchitectureRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAMBlockDiagram(1)RamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAMBlockDiagram(2)RamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAMCoreArchitectureRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAMAddressRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAMCoreArchitectureRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidential16bitDRAMCoreRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAMDataPathRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialDRAM1T-1CstructureRamaxelTechnologyLimitedRamaxelTechnologyLimitedConfidentialRAS:rowaddressstrobeCAS:columnaddressstrobeWE:writeenableAddress:codetoselectmemorycelllocationDQ(I/O):bidirectionalchanneltotransferandreceivedataDRAMcell:storageelementtostorebinarydatabitRefresh:theactiontokeepdatafromleakageActive:sensedatafromDRAMcellPrecharge: