17IntroducethePCBLayout

1IntroducethePCBLayoutPresentedbyNinaMiaoNDC2004-02Ver.2.02PCBLayoutSystem1.Padstack2.ComponentSymbols3.BoardDesign4.ImportingLogicInformationintoAllegro5.SettingDesignConstraints6.ComponentPlacement7.Routing8.Via9.TestPoint31.Padstack1.1Createaflashsymbol1.2Createpadstacks1.3AnatomyofaPadstack1.4PadstackDetails41.Padstack(Cont.)1.1Createaflashsymbolusedforthermalreliefs.Athermalreliefisaspecialpatternusedwhereconnectionsaremadetoanembeddedplanethatallowsheattoconcentratenearapinorviaduringthesolderingprocess.51.Padstack(Cont.)1.2Createpadstacksforanumberoftypicalpinsanddevicetypes:a.Createapadstackforathrough-holepin.b.Createapadstackforpin1ofathrough-holepin.c.Createapadstackforasurface-mounteddevice.61.Padstack(Cont.)1.3AnatomyofaPadstack71.Padstack(Cont.)1.4PadstackDetails82.Packagesymbol2.1Symboltypes92.Packagesymbol(Cont.)2.2.1Footprintsymbolsmodelthecomponentsthatareplacedontheprintedcircuitboard.2.2.2stylesoffootprintsincludingDIP,SOIC,PLCC,QFPandsoon.2.2.3Whencreatethefootprint,wewilldefineinformationsuchasdesignunits,numberofpins,pinspacing,padstackstouse,andsoforth.102.Packagesymbol(Cont.)2.2.4Packageoutline.113.BoardDesign3.1BoardOutline123.BoardDesign(Cont.)133.BoardDesign(Cont.)3.2Boardiscomposedof:143.BoardDesign(Cont.)3.3BoardStack-Up153.BoardDesign(Cont.)4.3milsPrepreg~48milsCore：FR44.5milsPrepreg1.FR4isaspecialmaterialofCore.2.Boardimpedance＝60Ω±10％。163.BoardDesign(Cont.)3.4Powerdivide174.ImportingLogicInformationintoAllegro4.1LayoutProcess4.2Bringtheschematicdata4.3Importlogicinformation4.3.1ConceptLogicImport4.3.2CaptureLogicimport4.3.3Third-PartyLogicImport184.ImportingLogicInformationintoAllegro(Cont.)4.1LayoutProcess194.ImportingLogicInformationintoAllegro(Cont.)4.2BringschematicdatafromtheConcepttool,Capturetool,orathird-partyfront-endtool.4.3SetupandimportlogicinformationintoAllegrofromoneofthethesethreeschematicenvironments:􀂄Concept-HDL􀂄Capture􀂄Third-party204.ImportingLogicInformationintoAllegro(Cont.)4.3.1ConceptLogicImport214.ImportingLogicInformationintoAllegro(Cont.)4.3.2CaptureLogicimport224.ImportingLogicInformationintoAllegro(Cont.)4.3.3Third-PartyLogicImport234.ImportingLogicInformationintoAllegro(Cont.)245.SettingDesignConstraints255.SettingDesignConstraints(Cont.)5.1Therearefourtypesofdesignrules:5.1.1SpacingRuleSet:Clearancesbetweenlines,pads,vias,andcopperareas(shapes)5.1.2PhysicalRuleSet:Linewidthandlayerrestrictions5.1.3DesignConstraints:Packagechecks,soldermaskchecksandnegativeplaneislandchecks265.SettingDesignConstraints(Cont.)5.1.4ElectricalConstraintSets:Performancecharacteristics(crosstalkandpropagationdelay).275.SettingDesignConstraints(Cont.)5.2Therearetwolevelsofdetailfordesignrules:5.2.1Standardrules:Describethemajorityofnetsinadesign.Theseglobalrulesareappliedtoallnets(allnetsarecreatedequal).5.2.2Extendedrules:Areperformancerelated,andareassignedonanet-by-netbasis.􀂄Timingandspeedconsiderations(netlengthandpropagationdelay)􀂄Noiseanddistortionconcerns(crosstalk,reflection,impedence).286.ComponentPlacement6.1Theprerequisitesformanualplacementare:6.1.1Symbols:Thepackagesymbolsandpadstacksrequiredforpartsinthenetlistmustexist.6.1.2Netlist:YoumustloadaschematicdatabaseintoanAllegrodesignfile(.brd).6.1.3Floorplanning:Youcancreatea“blockdiagram”ofthelogicalfunctionsthatneedtobearrangedontheboardbyusingRooms.296.ComponentPlacement(Cont.)6.2Componentplacementstrategy􀂄Createroomsforfloorplanning.􀂄Assignreferencedesignatorstopreplaceddevices.􀂄PlaceI/Obounddevices.􀂄Placecriticallogicfunctions.􀂄Evaluateandreviseplacement.􀂄Placebulkdecouplingandbypasscaps.􀂄Usereportstoaidplacementprocess.306.ComponentPlacement(Cont.)6.3Setdrawingparameters.􀂄Placethemechanicalsymbol.􀂄Addformatsymbols.􀂄Addpackagesymbols.􀂄Setcolorandvisibility.􀂄Definethecrosssection(layerstackup).317.Routing7.1InteractiveroutingmodesDefinenetpropertiesbeforeaddingetch.􀂄Commonnetpropertiesusedwithinteractiverouteare:MIN_LINE_WIDTHMIN_NECK_WIDTHNO_RATFIXED􀂄Addingsignalconnections􀂄Deletingsignalconnections􀂄Insertingvias.7.2AutomaticRoutingmodes328.1TypeofVia:􀂄throughvia􀂄blindvia􀂄buriedvia339.TestPoint9.1Bareboarda.Electricalcontinuitycheck(opensandshorts)b.PerformedafterfabricationAfterthephysicalboardhasbeenmanufactured,itistestedforcontinuitybythefabricationfacility,knownasbareboardtest.Thistestcheckstheconnectionsbetweenallcomponentpins,andensuresthatno“shorts”or“opens”exist.349.TestPoint(Cont.)9.2In-circuita.Logicalperformancecheckb.PerformedafterassemblyAftertheboardhasbeenassembled,itgoesthroughfurthertestingknownasin-circuittesting.In-circuittestingverifiesthattheboardandcomponentsareworkingtogetherasdesigned(knownasinputsandoutputs).359.TestPoint(Cont.)9.3SignaltestpointandGndtestpoint.9.4Atleast10mildistancebetweentestpointandthepinofcomponent.9.5Alltestpointsaremarkedwithatestpointsymbol.36Q&AThankyou!