74HC4020DB中文资料

DATASHEETProductspecificationFileunderIntegratedCircuits,IC06September1993INTEGRATEDCIRCUITS74HC/HCT402014-stagebinaryripplecounterForacompletedatasheet,pleasealsodownload:•TheIC0674HC/HCT/HCU/HCMOSLogicFamilySpecifications•TheIC0674HC/HCT/HCU/HCMOSLogicPackageInformation•TheIC0674HC/HCT/HCU/HCMOSLogicPackageOutlinesSeptember19932PhilipsSemiconductorsProductspecification14-stagebinaryripplecounter74HC/HCT4020FEATURES•Outputcapability:standard•ICCcategory:MSIGENERALDESCRIPTIONThe74HC/HCT4020arehigh-speedSi-gateCMOSdevicesandarepincompatiblewiththe“4020”ofthe“4000B”series.TheyarespecifiedincompliancewithJEDECstandardno.7A.The74HC/HCT4020are14-stagebinaryripplecounterswithaclockinput(CP),anoverridingasynchronousmasterresetinput(MR)andtwelvefullybufferedparalleloutputs(Q0,Q3toQ13).ThecounterisadvancedontheHIGH-to-LOWtransitionofCP.AHIGHonMRclearsallcounterstagesandforcesalloutputsLOW,independentofthestateofCP.Eachcounterstageisastatictoggleflip-flop.QUICKREFERENCEDATAGND=0V;Tamb=25°C;tr=tf=6nsNotes1.CPDisusedtodeterminethedynamicpowerdissipation(PDinμW):PD=CPD×VCC2×fi+∑(CL×VCC2×fo)where:fi=inputfrequencyinMHzfo=outputfrequencyinMHz∑(CL×VCC2×fo)=sumofoutputsCL=outputloadcapacitanceinpFVCC=supplyvoltageinV2.ForHCtheconditionisVI=GNDtoVCCForHCTtheconditionisVI=GNDtoVCC-1.5VORDERINGINFORMATIONSee“74HC/HCT/HCU/HCMOSLogicPackageInformation”.SYMBOLPARAMETERCONDITIONSTYPICALUNITHCHCTtPHL/tPLHpropagationdelayCL=15pF;VCC=5VCPtoQ01115nsQntoQn+166nsMRtoQn1719nsfmaxmaximumclockfrequency10152MHzCIinputcapacitance3.53.5pFCPDpowerdissipationcapacitanceperpackagenotes1and21920pFSeptember19933PhilipsSemiconductorsProductspecification14-stagebinaryripplecounter74HC/HCT4020PINDESCRIPTIONPINNO.SYMBOLNAMEANDFUNCTION9,7,5,4,6,13,12,14,15,1,2,3Q0,Q3toQ13paralleloutputs8GNDground(0V)10CPclockinput(HIGH-to-LOW,edge-triggered)11MRmasterresetinput(activeHIGH)16VCCpositivesupplyvoltageFig.1Pinconfiguration.Fig.2Logicsymbol.Fig.3IEClogicsymbol.fpageMGA829RCTR1497546131214151230313CT=0CTSeptember19934PhilipsSemiconductorsProductspecification14-stagebinaryripplecounter74HC/HCT4020Fig.4Functionaldiagram.Fig.5Logicdiagram.FUNCTIONTABLENotes1.H=HIGHvoltagelevelL=LOWvoltagelevelX=don’tcare↑=LOW-to-HIGHclocktransition↓=HIGH-to-LOWclocktransitionINPUTSOUTPUTSCPMRQ0,Q3toQ13↑↓XLLHnochangecountLFig.6Timingdiagram.September19935PhilipsSemiconductorsProductspecification14-stagebinaryripplecounter74HC/HCT4020DCCHARACTERISTICSFOR74HCFortheDCcharacteristicssee“74HC/HCT/HCU/HCMOSLogicFamilySpecifications”.Outputcapability:standardICCcategory:MSIACCHARACTERISTICSFOR74HCGND=0V;tr=tf=6ns;CL=50pFSYMBOLPARAMETERTamb(°C)UNITTESTCONDITIONS74HCVCC(V)WAVEFORMS+25-40to+85-40to+125min.typ.max.min.max.min.max.tPHL/tPLHpropagationdelayCPtoQ0391411140282417535302104236ns2.04.56.0Fig.7tPHL/tPLHpropagationdelayQntoQn+122867515139519161102219ns2.04.56.0Fig.7tPHLpropagationdelayMRtoQn552016170342921543372255143ns2.04.56.0Fig.8tTHL/tTLHoutputtransitiontime19767515139519161102219ns2.04.56.0Fig.7tWclockpulsewidthHIGHorLOW801614114310020171202420ns2.04.56.0Fig.7tWmasterresetpulsewidthHIGH801614176510020171202420ns2.04.56.0Fig.8tremremovaltimeMRtoCP50109622651311751513ns2.04.56.0Fig.8fmaxmaximumclockpulsefrequency6.0303530921094.824284.02024MHz2.04.56.0Fig.7September19936PhilipsSemiconductorsProductspecification14-stagebinaryripplecounter74HC/HCT4020DCCHARACTERISTICSFOR74HCTFortheDCcharacteristicssee“74HC/HCT/HCU/HCMOSLogicFamilySpecifications”.Outputcapability:standardICCcategory:MSINotetoHCTtypesThevalueofadditionalquiescentsupplycurrent(ΔICC)foraunitloadof1isgiveninthefamilyspecifications.TodetermineΔICCperinput,multiplythisvaluebytheunitloadcoefficientshowninthetablebelow.ACCHARACTERISTICSFOR74HCTGND=0V;tr=tf=6ns;CL=50pFINPUTUNITLOADCOEFFICIENTCPMR0.851.10SYMBOLPARAMETERTamb(°C)UNITTESTCONDITIONS74HCTVCC(V)WAVEFORMS+25-40to+85-40to+125min.typ.max.min.max.min.max.tPHL/tPLHpropagationdelayCPtoQ018364554ns4.5Fig.7tPHL/tPLHpropagationdelayQntoQn+18151922ns4.5Fig.7tPHLpropagationdelayMRtoQn22455668ns4.5Fig.8tTHL/tTLHoutputtransitiontime7151922ns4.5Fig.7tWclockpulsewidthHIGHorLOW2072530ns4.5Fig.7tWmasterresetpulsewidthHIGH2082530ns4.5Fig.8tremremovaltimeMRtoCP1021315ns4.5Fig.8fmaxmaximumclockpulsefrequency25472017MHz4.5Fig.7September19937PhilipsSemiconductorsProductspecification14-stagebinaryripplecounter74HC/HCT4020ACWAVEFORMSPACKAGEOUTLINESSee“74HC/HCT/HCU/HCMOSLogicPackageOutlines”.Fig.7Waveformsshowingtheclock(CP)tooutput(Qn)propagationdelays,theclockpulsewidth,theoutputtransitiontimesandthemaximumclockfrequency.(1)HC:VM=50%;VI=GNDtoVCC.HCT:VM=1.3V;VI=GNDto3V.Fig.8Waveformsshowingthemasterreset(MR)pulsewidth,themasterresettooutput(Qn)propagationdelaysandthemasterresettoclock(CP)removaltime.(1)HC:VM=50%;VI=GNDtoVCC.HCT:VM=1.3V;VI=GNDto3V.