搜索
loginid=liuye@alonginfo.com,time=2013-05-1415:23:19,ip=113.87.121.179,doctitle=MT6572PCBDesignGuidelines--TraditionalChinese_V0_4.pdf,company=Along_WCXCopyright©MediaTekInc.Allrightsreserved.MT6572PCB設計規範©2013MediaTekInc.ThisdocumentcontainsinformationthatisproprietarytoMediaTekInc.Unauthorizedreproductionordisclosureofthisinformationinwholeorinpartisstrictlyprohibited.Specificationsaresubjecttochangewithoutnotice.V0.4MEDIATEKCONFIDENTIALFORliuye@alonginfo.comUSEONLYloginid=liuye@alonginfo.com,time=2013-05-1415:23:19,ip=113.87.121.179,doctitle=MT6572PCBDesignGuidelines--TraditionalChinese_V0_4.pdf,company=Along_WCX設計規範版本修訂記錄版本日期描述編輯者V0.12013/01/04初版(LPDDR1only)MizarChang,CarolChen,ZhuanningCao,Wanda,Ivy,YingLiu,FKPan,CharlesChenV0.22013/01/181.P10疊構(PCBStack-up)建議:6層1階修改2.P21~P33AddLPDDR2guidelines3.P60新增MIPI走線規則4.P61Charge文字敘述修改5.P67,P68RFTrace(1-1/3)&(2-1/3)update圖片6.P70RF-Trace3/3update圖片7.P75增加(CrystalGPS)走線規則8.P5,P8,P12,P17,P19,P20,P35,P36,圖面與文字修正MizarChang,CarolChen,ZhuanningCao,Wanda,Ivy,YingLiu,FKPan,CharlesChenV0.42013/04/101.P10疊構(PCBStack-up)建議:6層1階修改2.P18,P19更新LPDDR1C/A在L2的走線規則3.P36更新6層疊構中VIO_EMIPWR/GNDPlane設計規則4.P28,P30,P33,P37,P39,圖面與文字修正MizarChang,CarolChen,ZhuanningCao,Wanda,Ivy,YingLiu,FKPan,CharlesChen2013/4/10Copyright©MediaTekInc.Allrightsreserved.1MEDIATEKCONFIDENTIALFORliuye@alonginfo.comUSEONLYloginid=liuye@alonginfo.com,time=2013-05-1415:23:19,ip=113.87.121.179,doctitle=MT6572PCBDesignGuidelines--TraditionalChinese_V0_4.pdf,company=Along_WCX綱目▪封裝–MT6572芯片外形尺寸–MT6572Footprint設計–MT6572重要信號分佈圖▪一般設計建議–疊構(PCBstack-up)建議–CommonRulesandViaType–PlacementNotes–MT6572fanout▪High-speeddigital設計建議–LPDDR1/LPDDR2/PDN–PDNdesignforCPU▪其它設計建議–RFIQ-USB-MHL-MIPI-Charger–Camera-SIMCard-T-CARD–DifferentialPairLayoutSuggestion–MT6627(BT/FM/WiFi/GPS)–MT6323(PMU)2013/4/10Copyright©MediaTekInc.Allrightsreserved.2MEDIATEKCONFIDENTIALFORliuye@alonginfo.comUSEONLYloginid=liuye@alonginfo.com,time=2013-05-1415:23:19,ip=113.87.121.179,doctitle=MT6572PCBDesignGuidelines--TraditionalChinese_V0_4.pdf,company=Along_WCX綱目▪封裝–MT6572芯片外形尺寸–MT6572Footprint設計–MT6572重要信號分佈圖▪一般設計建議–疊構(PCBstack-up)建議–CommonRulesandViaType–PlacementNotes–MT6572fanout▪High-speeddigital設計建議–LPDDR1/LPDDR2/PDN–PDNdesignforCPU▪其它設計建議–RFIQ-USB-MHL-MIPI-Charger–Camera-SIMCard-T-CARD–DifferentialPairLayoutSuggestion–MT6627(BT/FM/WiFi/GPS)–MT6323(PMU)2013/4/10Copyright©MediaTekInc.Allrightsreserved.3MEDIATEKCONFIDENTIALFORliuye@alonginfo.comUSEONLYloginid=liuye@alonginfo.com,time=2013-05-1415:23:19,ip=113.87.121.179,doctitle=MT6572PCBDesignGuidelines--TraditionalChinese_V0_4.pdf,company=Along_WCXMT6572芯片外形尺寸2013/4/10Copyright©MediaTekInc.Allrightsreserved.4▪Packageinfo.–Bodysize:10.6mmx10.6mmx1.1mmmax.–Ballpitch:0.4mm–Balldiameter:0.25mm–Ballcount:428BOTTOMVIEWPin1TOPVIEWMEDIATEKCONFIDENTIALFORliuye@alonginfo.comUSEONLYloginid=liuye@alonginfo.com,time=2013-05-1415:23:19,ip=113.87.121.179,doctitle=MT6572PCBDesignGuidelines--TraditionalChinese_V0_4.pdf,company=Along_WCXMT6572Footprint設計2013/4/10Copyright©MediaTekInc.Allrightsreserved.5CenterPadMaskOpeningMT6572的封裝焊盤使用copperdefined設計方式。▪鋼網開口設計，建議使用0.25mm方形，做0.075導R角。(如右圖綠色區域)如右圖所示，焊盤皆為copperdefined。Pad直徑0.25mm，soldermask為0.325mm。MT6572正下方，via1-2盲孔建議使用0.1/0.25mm(4/10mil)，以提升SMT良率MEDIATEKCONFIDENTIALFORliuye@alonginfo.comUSEONLYloginid=liuye@alonginfo.com,time=2013-05-1415:23:19,ip=113.87.121.179,doctitle=MT6572PCBDesignGuidelines--TraditionalChinese_V0_4.pdf,company=Along_WCX2013/4/10Copyright©MediaTekInc.Allrightsreserved.6MT6572重要信號分佈圖2013/4/106PLCDRFI/QToMT6323MAINPOWER&GNDA1LPDDR1/LPDDR2ToMT6627SIMCardMIPI-TXUSBMIPI-RXPCAMMSDCNAND/EMMCMEDIATEKCONFIDENTIALFORliuye@alonginfo.comUSEONLYloginid=liuye@alonginfo.com,time=2013-05-1415:23:19,ip=113.87.121.179,doctitle=MT6572PCBDesignGuidelines--TraditionalChinese_V0_4.pdf,company=Along_WCX綱目▪封裝–MT6572芯片外形尺寸–MT6572Footprint設計–MT6572重要信號分佈圖▪一般設計建議–疊構(PCBstack-up)建議–CommonRulesandViaType–PlacementNotes–MT6572fanout▪High-speeddigital設計建議–LPDDR1/LPDDR2/PDN–PDNdesignforCPU▪其它設計建議–RFIQ-USB-MHL-MIPI-Charger–Camera-SIMCard-T-CARD–DifferentialPairLayoutSuggestion–MT6627(BT/FM/WiFi/GPS)–MT6323(PMU)2013/4/10Copyright©MediaTekInc.Allrightsreserved.7MEDIATEKCONFIDENTIALFORliuye@alonginfo.comUSEONLYloginid=liuye@alonginfo.com,time=2013-05-1415:23:19,ip=113.87.121.179,doctitle=MT6572PCBDesignGuidelines--TraditionalChinese_V0_4.pdf,company=Along_WCXMT6572PCB疊構(Stack-up)建議▪PCB之總疊層厚度請勿超過1.0mm±10%。▪各層銅箔屬性、及中間夾層之厚度和材質請儘量遵照以下建議去規劃，以達最佳之電性設計。▪在”Layerdefinition”中，這裡只針對LPDDR1/2和CPU做建議。其中“空白”的部分可自行決定，若有空間，可用來做LPDDR1/2和CPU的PWR/GNDplane的補強。▪其它訊號之”Layerdefinition”請遵照這份PCBdesignguideline描述之設計規範進行設計即可。▪這邊共建議了以下幾種疊構：–4層1階–6層1階2013/4/10Copyright©MediaTekInc.Allrightsreserved.8MEDIATEKCONFIDENTIALFORliuye@alonginfo.comUSEONLYloginid=liuye@alonginfo.com,time=2013-05-1415:23:19,ip=113.87.121.179,doctitle=MT6572PCBDesignGuidelines--TraditionalChinese_V0_4.pdf,company=Along_WCX2013/4/10Copyright©MediaTekInc.Allrightsreserved.9疊構(PCBStack-up)建議:4層1階▪如果板厚需調整,請維持建議PP厚度,僅調整core厚度以達需求MEDIATEKCONFIDENTI