Quartus-II-时序约束方法

©2007AlteraCorporation—ConfidentialQuartusIISoftwareDesignSeries:TimingAnalysis©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation2常见术语的中文翻译Tsetup:建立时间Thold：保持时间Skew：传输时差,时钟歪斜Slack：余量Fmax：最大频率Inputmaximumdelay：输入最大延时Inputminimumdelay：输入最小延时Outputmaximumdelay：输出最大延时Outputminimumdelay：输出最小延时Maxdelay：最大延时MinDelay：最小延时Recoverytime：恢复时间Removaltime：移去时间Jitter：抖动©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation3TimeQuestAgendaIntroductiontoTimeQuestTimeQuestterminologyreviewUsingTimeQuestExampleApplication©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation4TimeQuestTimingAnalyzerNewtimingengineinQuartusIIProvidetiminganalysissolutionmeetingrequirementsofallusersFPGAdesignbackgroundASICdesignbackgroundEasy-to-useinterfaceStandardreporting&constraintterminologyScriptingemphasis©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation5TimeQuestTimingAnalyzer(cont.)Moreaccurateanalysisrise/falldelaysSDCSupportMoreadvanced&standardizedconstraintmethodologyEasilysupportsmorecomplexdesignsandanalysisComplexclockingschemesSource-synchronousdesigns©2007AlteraCorporation—ConfidentialValidatingPerformancewiththeTimeQuestStaticTimingAnalyzerTimeQuestTerminologyReview©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation7TimeQuestTerminologyReviewLaunch&latchedgesArrivaltimevs.requiredtimeSetup&holdanalysisSlackSDCterminology©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation8Path&AnalysisTypesThreetypesofPaths:1.ClockPaths2.DataPath3.AsynchronousPaths*ClockPathsAsyncPathDataPathAsyncPathDQCLRPREDQCLRPRETwotypesofAnalysis:1.Synchronous–clock&datapaths2.Asynchronous*–clock&asyncpaths*Asynchronousreferstosignalsfeedingtheasynchronouscontrolportsoftheregisters©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation9Setup&HoldSetup:TheminimumtimedatasignalmustbestableBEFOREclockedgeHold:TheminimumtimedatasignalmustbestableAFTERclockedgeDQCLRPRECLKThValidDATATsuCLKDATATogether,thesetuptimeandholdtimeformaDataRequiredWindow,thetimearoundaclockedgeinwhichdatamustbestable.©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation10Launch&LatchEdgesCLKREG1DQSETCLRREG2DQSETCLRComb.LogicCLKLaunchEdgeLatchEdgeDataValidDATALaunchEdge:theedgewhich“launches”thedatafromsourceregisterLatchEdge:theedgewhich“latches”thedataatdestinationregister(withrespecttothelaunchedge,typically1cycle)©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation11Launch&LatchEdgesLaunchEdge:Clockedgethatactivatesthesourceregisterinaregister-to-registerpathLatchEdge:ClockedgethatactivatesthedestinationregisterBACLKACLKBCLKACLKBTherelationshipbetweentheedgesisderivedfromtheuser-definedclocksettings©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation12DataArrivalTimeThetimefordatatoarriveataregister’sDinputTclk1TdataμTcoQQSETCLRDQQSETCLRDCLKTclk1Tclk2TdataμTcoμTsu/μThREG1REG2CLKREG1.CLKREG1.QREG2.DDataArrivalTime=launchedge+Tclk1+μTco+TdataLaunchEdge©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation13ClockArrivalTimeThetimeforclocktoarriveataregister’sclockinputQQSETCLRDQQSETCLRDCLKTclk1Tclk2TdataμTcoμTsu/μThREG1REG2CLKREG2.CLKTclk2ClockArrivalTime=latchedge+Tclk2LatchEdge©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation14DataRequiredTime-SetupTimesignalmustarriveatdestinationregistertobeproperlysampledQQSETCLRDQQSETCLRDCLKTclk1Tclk2TdataμTcoμTsu/μThREG1REG2CLKREG2.CLKTclk2μTsuDataRequiredTime=ClockArrivalTime–μTsuLatchEdge©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation15DataRequiredTime-HoldQQSETCLRDQQSETCLRDCLKTclk1Tclk2TdataμTcoμTsu/μThREG1REG2CLKREG2.CLKTclk2μThDataRequiredTime=ClockArrivalTime+μThLatchEdgeEarliesttimesignalcanarriveatdestinationregisterandnotinterferewithdatasampledonpreviousclockedge©2007AlteraCorporation—ConfidentialAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation16SlackSetupSlack=SetupRequiredTime–DataArrivalTimeHoldSlack=DataArrivalTime–HoldRequiredTimeSlackmustbepositivetoensureproperoperationEquationsworkforinternalandI/Opa