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1毕业设计(论文)基于FPGA的Viterbi译码器姓名：学院：专业：班级：指导教师：2摘要卷积编码是深度空间通信系统和无线通信系统中常采用的一种编码方式,广泛应用于卫星通信、无线通信等多种通信系统。在1967年，Viterbi提出了卷积码的Viterbi译码算法，它是一种卷积码的最大似然译码算法，通过寻找译码器接收序列和卷积编码器的输出序列的最大似然函数来得出译码结果。该算法译码性能好、速度快，并且硬件实现结构比较简单，是最佳的卷积码译码算法。随着可编程逻辑技术的不断发展，使用FPGA实现viterbi译码器的设计方法逐渐称为主流。因此设计viterbi译码器，使其能够满足多种通信系统的应用要求，具有重要的现实意义。本文的主要内容是基于FPGA的Viterbi译码器设计。在对viterbi译码算深入研究过程中，重点研究了Viterbi译码器各个模块的主要功能。在本设计中，采用了硬判决计算输入信息码元与各状态的期望码元之间的分支度量值，用串行加比选碟型算法来寻找编码器网格图上的幸存路径，用回溯法(trace-back)算法来对幸存路径做处理得到译码输出，用乒乓方式对幸存路径进行存储。本论文设计输入是采用硬件描述语言VHDL来完成的，通过在各种EDA工具下的仿真和综合，验证了本文所设计的Viterbi译码器的正确性和实用性。关键词：卷积码；维特比；译码器；现场可编程门阵列3ABSTRACTConvolutionalcodinghasbeenusedincommunicationsystemsincludingdeepspacecommunicationsandwirelesscommunications,whicharewidelyusedinsatellitecommunicationsandwirelesscommunication.TheViterbialgorithm,proposedin1967byViterbi,isamaximum-likelihoodalgorithmforconvolutionalcodes.TheViterbidecoderattemptstofindthemaximum-likelihoodfunctionofthedecodedcodewordagainstreceivedcodeword.Thismethodisbetterdecodingperformance,fast,andrelativelysimplehardwarearchitecture,isthebestconvolutionalcodedecodingalgorithm.Withthecontinuousdevelopmentofprogrammablelogictechnology,theuseofFPGAimplementationviterbidecoderdesignmethodcalledmainstreamgradually.Therefore,thedesignviterbidecodersothatitcanmeettheapplicationrequirementsofavarietyofcommunicationsystems,hasimportantpracticalsignificance.ThemaincontentofthispaperistodesignaViterbidecoderwithFPGAtechnology.In-depthstudyoftheviterbidecodingcalculationprocess,focusingonthemainfunctionsofeachmoduleViterbidecoder.Inthispaper,theparallelACS(add-compare-select)Butterflyalgorithmisusedtofindthesurvivorpathinencodertrellis.Wealsousetrace-backalgorithmtodisposethesurvivorpathandreceivethedecodedresults.Inaddition,thebehaviorofadesignisdescribedinVHDL.TheemulatedandsynthesizedresultsofthisdesignarereceivedbyallkindsofEDAtools.ThroughtheseresultstheViterbidecoder’scorrectnessandpracticabilitycanbevalidated.Keywords：ConvolutionalCode;Viterbi;Viterbi;FPGA4目录绪论............................................................................................................................5第一章纠错码的基本原理........................................................................................71.1差错控制的基本方式......................................................................................71.2纠错编码的基本原理......................................................................................81.3纠错编码的分类..........................................................................................10第二章卷积码和Viterbi算法.................................................................................122.1卷积码基础..................................................................................................122.1.1卷积码编码原理..................................................................................122.1.2卷积码的描述......................................................................................142.2Viterbi译码原理..........................................................................................172.2.1Viterbi算法描述....................................................................................172.2.2Viterbi算法举例....................................................................................182.2.3Viterbi译码器的特点...........................................................................22第三章Viterbi译码的FPGA实现.........................................................................233.1Viterbi译码器的基本结构........................................................................233.2分支度量模块（BMU）...............................................................................253.3加比选模块(ACS).........................................................................................263.3.1状态间的蝶形运算关系.......................................................................263.3.2加比选的实现方式............................................................................293.3.3溢出处理..............................................................................................293.4路径度量存储模块（PMU）.....................................................................303.5幸存路径寄存模块（SMU）.......................................................................313.5.1寄存器交换法......................................................................................323.5.2回溯法..................................................................................................333.6回溯模块(TBU).............................................................................................34第四章Viterbi译码器的设计与仿真结果..........................................................364.1卷积码编码器设计......................................................................................364.2Viterbi译码器的设计.................................................................................37第五章结束语............................................................................................................39参考文献.........................................................................................................