2.-Analog-layout-design

2.AnaloglayoutdesignKanazawaUniversityMicroelectronicsResearchLab.AkioKitagawaWellstructurespsubstratensubstratep-orn-substratep-substraten-wellprocessp-wellprocessTwin-wellprocess(Theimpurityconcentrationisoptimized.)Triple-wellprocess(Thewellscanbeelectricallyisolatedeachother.)p-welln-wellp-welln-wellp-welln-welln-well2Deepn-well(Triple-wellprocess)TriplewellprocessTwin-wellprocessdeepn-welln-wellretrogradep-wellactive(MOSFET)active(MOSFET)n-welldeepn-wellp-substraten-welln-wellpFOXFOXp-substraten-wellpFOXFOXactiveactive3Shallowtrenchisolation(STI)FOX:FieldOxide(Thickness=100nm)GOX:GateOxide(Thickness=severalnm)FOXFOXFOXActiveActiveFieldFieldFieldGOXGOXSiSiO2MOSFETisolationisolationisolationMOSFETVDDcannotinverttheMOSinterface.4Layoutandcrosssection(Twinwell)poly(G)SDcontactContactn-activen-wellWnLncontactp-substraten+n+FieldOxideGDSBp+DFOXp-activep-chMOSFETpoly(G)SDn-activep-activeBn-wellp+p+GDSBn+DFOXFOXLpBWpn-chMOSFET5Layoutandcrosssection(Triplewell)poly(G)SDcontactContactn-activen-wellWnLncontactp-substraten+n+FieldOxideGDSBp+DFOXp-activepoly(G)SDn-activep-activeBn-wellp+p+GDSBn+DFOXFOXLpBWpdeepn-wellp-chMOSFETn-chMOSFET6Layers•LayernumbersareassignedtoWell,Active,Poly,Contact,Metal,Via,SilicideProtect,andDummy,respectively.•Somelayerisautomaticallygeneratedfromthepatternonthedrawnlayer.–ex.FOXandGOXisgeneratedfromthepatternontheactivelayer.polymetal-1contactn-active(n+)n-wellp-active(p+)via-1metal-2Legendoflayerspolyp-subn+p+p+n-wellcontactlayermetal-1layervialayermetal-2layerLayoutCrosssectionpolylayerp-activelayern-activelayern-welllayerFOX7DesignRules•Semiconductorfoundryallowsthedesignerstodesignonlythelayoutpatternonthetopview.–Thethicknessoflayersarefixedbythesemiconductorfoundry.•Thedesignershavetodesignthelayoutaccordingtodesignruleswhichisfixedforeachtechnology.Thepurposeofdesignruleisasfollows.–Warrantyofdimensionalprecisioninmicrofabrication–Warrantyofprecisiononelectricalcharacteristics–Preventionoflatch-up(NOTE)triggeredbyparasiticbipolar-transistors•DesignruleviolationisautomaticallydetectedandreportedinDRC(DesignRuleCheck).•Asemiconductorcompanyacceptsonlythedesignthatispassedthespecifieddesignrules.NOTE:Latch-upTheinadvertentcreationofalow-impedancepathbetweenthepowersupplyrailsofaCMOScircuit,triggeringaparasiticpnpnornpnpstructure.8Exampleofdesignrules(1)22211p-active22poly-12221122Metal-1Via-1contactpolyrulemin.width=2min.spacing2active(p+,n+)rulemin.width=2min.spacingtowell=2(inside)min.spacingtowell=1(outside)min.spacingtopoly=1metal-1rulemin.width=2min.spacing=2min.extensionbeyondcontact=1min.extensionbeyondvia-1=1n-well9GeometryRulesExampleofdesignrules(2)10MinimumDensityRulesAntennaRules(Process-InducedDamageRules)FinefeaturedprocessesutilizeCMP(Chemical-MechanicalPolishing)toachieveplanarity.EffectiveCMPrequiresthatthevariationsinfeaturedensityonalayerberestricted.TheAntennaRulesdealwithprocessinducedgateoxidedamagecausedwhenexposedpoly-siliconandmetalstructures,connectedtoathinoxidetransistor,collectchargefromtheprocessingenvironment(e.g.,reactiveionetch)anddeveloppotentialssufficientlylargetocauseFowlerNordheimcurrenttoflowthroughthethinoxide.Therulesrequirethattheareaofthepolysiliconandmetaloverfieldoxidedividedbytheareaofthetransistorgate(thinoxidearea)mustbelessthanNp(whereNpisalimitthatdependsontheprocessandondesigntargets).SGSF(poly)SF(M1)ܰ௣൐ܵிܵீVerificationsofthelayoutdesign•DRC(DesignRuleCheck)–Detectionofthedesignruleviolation•ERC(ElectricalRuleCheck)–Detectionoftheopen/shorterror•LVS(LayoutVSSchematic)–EquivalencecheckingbetweenlayoutandschematicThelayoutdesigncheckerhasabatchprocessingmodeandinteractivemode.11Influenceoncircuitperformanceofthelayout•Frequencyresponseinhigh-frequencyregion–Theparasiticresistanceandtheparasiticcapacitanceraiseanunintendedpoleandzero.–ThelonginterconnectactsasaparasiticinductororLCresonator.•Precisionofthecircuitoperation–CommoncentroidlayoutofMOSFET,C,andRcanimprovetheproductiontoleranceandmismatch.–Symmetriclayoutofinterconnectcanimprovestheproductiontoleranceandskewofthedigitalsignal(delay)andanalogsignal(phaselag).•Noiseandjittercharacteristics–Theparasiticresistance,especiallypoly-Si,actasathermalnoisesource.–Theparallelplacementofinterconnectraiseacrosstalkofsignals.12(1)LayoutoftheMOSFET13LayoutsampleofMOSFETpolymetal-1contactn-active(n+)n-wellp-active(p+)via-1metal-2n-chp-chDGSBDGSB14DGSParasiticofMOSFET•LongW:largetimeconstantofgatepoly-Si•LongW:largethermalnoiseofgatepoly-Si•LongLD,LS:largeparasiticcapacitanceandresistanceofdrain/sourcearea•Fewnumberofcontact:ShiftorfluctuationofsubstratepotentialLW□RRGDLWjCLongWLDLCgsWLParasiticGateresistance(R□:sheetresistance)DrainjunctioncapacitanceGate-SourcecapacitanceHowcanyoudesigntheMOSFETwithlargerW?LSBSLWjCDGSB15FingeredMOSFETW/4mgR1LW□MOFETshouldbesectionedtoreducethegateresistance.DSAbutmentHigh-performanceMOSFETarraygsdsmdVdIyg21gm:trans-conductanceThisconditionisoftenmetinthecaseofW/L20.W/L10isrecommended.Multiply=4(W/4ｘ4)FingerBG16Reductionofthedrainjunctioncapacit