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第七讲DraculaLVSLPE&Postsim分层设计李福乐lifule@tsinghua.edu.cnOutline•LVS的常用设置与错误类型•LPE/PRE版图寄生提取•后仿真•分层设计的几个问题LVSInternalFlowReaddatabaseTopcellnameExpanddataFromtopExtractdeviceandparametersFilterunuseddeviseReducedeviceasspecifiedBuiltmapofcorrespondenceTracefrompadsBuildDeviceAndnodemapsComparisonandOutputFilterunuseddevise…*descriptionsystem=gds2…filter-lay-opt=BCDEHJKORfilter-sch-opt=BCDEHJKOR…在lvscommandfile中的设定语句…Bgateisfloating,notconnecttoanypadthroughasource/drainCgateconnecttopowerorgroundandeitherthesourceordrainisfloatDgateisfloating,S/DnetshaveonlyaPOWERpathandnopathstoanypadEgateisfloating,S/DnetshaveonlyaGNDpathandnopathstoanypadFMOS[N]devicesthathavethegatetiedtoaGROUNDGMOS[P]devicesthathavethegatetiedtoaPOWERHwithboththesourceanddrainnetstiedtothePOWERFilterunuseddevise…*descriptionsystem=gds2…filter-lay-opt=BCDEHJKORfilter-sch-opt=BCDEHJKOR…在lvscommandfile中的设定语句IwithboththesourceanddrainnetstiedtotheGROUNDJgatetiedtoeitherPOWERorGNDandsourceanddraintiedtogetherKwithsourceanddrainhavingnopathstoanypadLeithersourceordrainisfloatingRresistorsanddiodswithatleastonefloatingterminalUboththesourceanddrainarefloatingZfloatingbipolartransistors,diods,andresistors…LVSInitialNodePairs•LVScomparisonusingtextextractedfromtheschematicandlayoutasastartingpoint•LVSresultheavilyrelyonthematchingofinputlabels•UseCPOINT-FILEcommand(in*Descriptionblock)tospecifythelabelmatchingoflayoutandschematic…*Description…CPOINT-FILE=INITNAME.TXTInINITNAME.TXT:LayoutnameSchematicnameinvingndvss……现在用的lvs文件中没有这个command，要用的自己填加LVSCheckOption…;lvscheckslvschk[xre]lpercent=0wpercent=0resval=1capval=1…在lvscommandfile中的设定AsmashesseriescapacitaorsCfromsCMOSgatessuchasINVERTORs,NORs,NANDs,AOIs,andOAIsEusessizeinfomationtomatchMOS,BJTandresistorparalleldevicesFfilterstheunusedMOSdevices,forexample,gatearraysGfiltersboththeschematicandthelayoutinthesamewayKkeepsparalledevicesunsmashedLsameastheCoptionexpectdoesnotformAOIandOAIgatesOformsparallesandseriesMOSsturucturesevenifneitherisconnectedtopowerorgroundPcheckstheELEMENTcapacitor'spolarityLVSCheckOption…;lvscheckslvschk[xre]lpercent=0wpercent=0resval=1capval=1…在lvscommandfile中的设定RsmashesseriesresistorsSsmashesMOSsplit-gatesthatareformedasSUPIorSDWIdevicestoasingleSUPorSDWdevice,respectivelyUreportsinthedescrepancyfile(.LVS)onlytheunmatchedschematicandunmatchedlayoutdevicesonmatchednodes(type4,5,and6LVSerrors)Xcarryesoutthecomparisonatthetaransistorlevel(thatis,noswapallowed)Xdon'tusewithSorLoption.Zrandomlymatchesdeviceswithacommonmatchesterminalandotherterminalsfloating,andfiltersoutdeviceswithpathtoanytextpads所以在task1:layout的电阻合并成1个了LVSDeviceReduction•DraculaiscapableofperformingLVSuptogatelevel•Gateinformationisextractedfromlayoutbydevicereduction•Gateinformationisextractedstage-by-stage•Primitivestructuresbydeviceextractioninclude:MOS,BJT,Res,DioandCapLVSDeviceReductionSecondLevelStructurePUPOut,IN1,IN2,…SUPOut,IN1,IN2,…LVSDeviceReductionSecondLevelStructurePDWOut,IN1,IN2,…SDWOut,IN1,IN2,…LVSDeviceReductionGateLevelStructurePUPIout1,IN1,IN2SUPOut,IN3,out1AOIOut,IN1,IN2,IN3SDWIout2,IN1,IN2PDWOut,IN3,out2LVSComparisonOptionProhibitInputSwappingLVSCHK[x]ReduceSeriesResistorsLVSCHK[r]ProhibitparallelReductionLVSCHK[k]LVSComparisonOptionReduceSeriesCapacitorsLVSCHK[a]SeriesMOSReductionLVSCHK[s]CMOSGateReductionLVSCHK[c]LVSCHK[l]L不能做到AOI和OAILVSParameterComparison…;lvscheckslvschk[xre]lpercent=0wpercent=0resval=1capval=1…SpecifythevaluetoleranceforparametercomparisonLpercent:MOSlengthratioWpercent:MOSwidthratioResval:resistorvalueratioCapval:capacitorvalueratioW/l-percent:MOSaspectratioweffect=0.6:CornereffecttoorthogonallybentgateLVSParameterComparison…;lvscheckslvschk[xre]lpercent=0wpercent=0resval=20capval=1例：将lvs中的resval改为20，重新对上一讲的例子task1做LVS检查，看修改前后的错误报告修改前的lvspr.lvs…1*************************************************************DISCREPANCYPOINTSLISTING*************************************************************************************DISCREPANCY1*********************DEV2RESRP----RR0:DEV6RESP2:X=-35.60Y=9.70OUT,VDD!OUT,VDD!SUB-TYPE=RPSUB-TYPE=P2VALUE=15000.0VALUE=13570.5TOTAL1DISCREPANCYPOINTSREPORTED这部分给出了schematic与layout不一致的地方：电阻模型名和阻值不一致！修改后的lvspr.lvs…1*************************************************************DISCREPANCYPOINTSLISTING*************************************************************************************DISCREPANCY1*********************DEV2RESRP----RR0:DEV6RESP2:X=-35.60Y=9.70OUT,VDD!OUT,VDD!SUB-TYPE=RPSUB-TYPE=P2TOTAL1DISCREPANCYPOINTSREPORTED由于15k和13.57k之差小于resval规定的20%，所以认为阻值通过LVSprintf.lvsLVSDebug•LVS报告在lvspr.lvs中其结构和内容上一讲已经通过例子来介绍过•LVSerror比DRCerror要难以debug•若设计中有子单元，一般先检查底层子单元，待其全部正确后再检查顶层单元•LVS结果与指定的pin,label等密切相关，所以在指定时一定不要弄错•很多error都是相关的，一个error可能会连锁导致很多error，故修正一个后马上重做LVS•要debugLVSerror，须熟知errortypes，所有的errortype可在矛盾点列表(Discrepancypointlisting)中查看LVSErrorTypesType1:MATCHEDNODETONODEVICEType2:MATCHEDDEVICETOUNMATCHEDNODE总共15种errortypesLVSErrorTypesType3:INCONSISTENTLYMATCHEDDEVICEType4:MatchedNodetoExtraLayoutDevicesLVSErrorTypesType5:MatchedNodetoExtraSc