SMI传感器AN05-001应用笔记

整理文档很辛苦,赏杯茶钱您下走!

免费阅读已结束,点击下载阅读编辑剩下 ...

阅读已结束,您可以下载文档离线阅读编辑

资源描述

SILICONMICROSTRUCTURESINCORPORATEDAN05-001NotesforDigitalCommunicationwithSM5800SeriesPartsAPPLICATIONNOTE2005SMISiliconMicrostructures,Inc.♦1701McCarthyBlvd.♦Milpitas,CA95035♦USATel:408-577-0100♦Fax:408-577-0123♦Sales@si-micro.com♦(I2C)Businterfaceforalldigitalcommunication.UsingtheI2Cbusthecorrecteddigitalpressureanddigitaltemperaturevaluesareaccessedfromonboardmemoryregisters.DIGITALCOMMUNICATIONBASICSTheI2Cbusinterfaceutilizesatwo-wiremethodforcarryinginformationbackandforthbetweenintegratedcircuitdevicesconnectedtothebus.Thetwo-wiremethodiscomprisedofabi-directional,8-bitserialdata(SDA)lineprovidingthepathfordatatransfersandaserialclock(SCL)lineforsynchronizingthedatatransfers.AMasterdeviceintheformofapersonalcomputerormicrocontrollerinitiatesandterminatesdatatransfersontheSDAlineandgeneratestheclocksignalontheSCLline.ASlavedevice(whichrepresentstheSM5800seriesproduct)receivesrequestsfromtheMasterandtransmitsdataaccordingtotherequest.WhenmultipleSlavedevicesareconnectedtothebus,eachSlavemusthaveauniqueaddressandtheMastermustusethisuniqueaddresswhenperformingdatatransferswithaparticularSlave.AdiagramoftheI2CbuswithaMasterandmultipleSlaves(orSM5800parts)isshowninFigure1.MasterSlave1Slave2Slave3Figure1.MultipleSM5800seriesdevicesconnectedtotheI2CbusDATATRANSFERThedatatransferprocessbeginswiththeMasterissuingaSTART(S)command,whichalertsallSlavedevicesofthependingtransferrequest.TheMasterthenspecifieswhichSlavedevicetocommunicatewithandhowthedatawillflowbetweentheMasterandSlave.Next,theMasterwaitsfortheaddressedSlavetorespond.WhenthedesiredSlaveresponds,theMasterandSlavebegintheprocessoftransmittingdatabackandforth.ThetransferprocessendswiththeMasterissuingaSTOP(P)command.Figure2providesadiagramshowingasimpledatatransfersequence.START&STOPCONDITIONSInitiatedbytheMaster,aSTARTconditionedisidentifiedbyaHIGHtoLOWtransitionoftheSDAlinewhilemaintainingastableHIGHconditionontheSCLline.AlldatatransfermustbeginwithaSTARTconditionandthebuslinesareconsideredbusyafteraSTARTconditionisissued.ToendthetransferofdatatheMasterinitiatesaSTOPcondition,whichisidentifiedbyaLOWtoHIGHtransitionoftheSDAlinewhilemaintainingastableHIGHconditionontheSCLline.AN05-001NotesforDigitalCommunicationwithSM5800SeriesPartsAPPLICATIONNOTE2005SMISiliconMicrostructures,Inc.♦1701McCarthyBlvd.♦Milpitas,CA95035♦USATel:408-577-0100♦Fax:408-577-0123♦Sales@si-micro.com♦(LSB)8SLAVEADDRESS(BEGINSWTHMSB)ACKDATA(BEGINSWTHMSB)PACKSCLSDAHIGHLOWHIGHLOWSTARTCONDITIONSTOPCONDITIONBITSBYTECOMPLETE,CLOCKHELDLOWUNITLRECEIVINGDEVICEISREADYFORNEXTOPERATIONFigure2.DiagramofasimpledatatransfersequenceDATAFORMAT&VALIDITYTheSDAlineisan8-bitdigitallineandthisdefinesthesizeofeachbytetransferred.AnacknowledgebitstartswiththeTransmitterreleasingtheSDAlineHIGHatthestartoftheclockcycleimmediatelyfollowingabytetransfer.TheReceivermustthenpulltheSDAlineLOWduringtheHIGHperiodofthesameclockcycle.Theset-upandholdtimesfortheSDAandSCLlinesareprovidedinAPPENDIXA.EverybytetransferredfromTransmittertoReceiverstartswiththemostsignificantbit(MSB).ValiddatatransfersonlyoccurduringtheHIGHperiodoftheSCLclock.IfaReceiverneedstimetocarryoutarequestbeforereceivinganotherbyte,itcanholdtheSCLlineLOW.TodothistheReceiverperformsaninternalinterrupttoholdtheSCLLOW,whichforcestheTransmittertowaitbeforesendingthenextbyte.Whenready,theReceiverreleasestheSCLlineanddatatransfercontinues.ADDRESSINGASLAVEDEVICEAllSlavedevicesmusthaveauniqueidentificationoraddress.ASlaveaddresscannotexceedalengthofsevenbits.TheSlaveaddresssharesspaceintheaddressbytewitharead/writebitandthemaximumlengthoftheaddressbyteiseightbits.Toconstructtheaddressbyte,placetheSlaveaddressattheMSBoftheaddressbyteandplacetheread/writebitattheleastsignificantbit(LSB).TheaddressbytealwaysfollowsaSTARTcondition.WhenanaddressbyteissentovertheSDAline,eachSlavecomparestheMSBofthisbytewithitsownuniqueaddress.TheSlavewiththematchingaddressbecomesactiveandrespondsbysendinganacknowledgebitalongtheSDAlinetotheMaster.HowtheSlaverespondstothenextbytetransmittedbytheMasterfollowingtheacknowledgementdependsontheread/writebit.WhentheLSBoftheaddressbyteis“1”theSlavetransmitsdatafortheMastertoread.WhentheLSBoftheaddressbyteis”0”theSlavewaitsfortheMastertowritedatatotheSlave.SILICONMICROSTRUCTURESINCORPORATEDAN05-001NotesforDigitalCommunicationwithSM5800SeriesPartsAPPLICATIONNOTE2005SMISiliconMicrostructures,Inc.

1 / 9
下载文档,编辑使用

©2015-2020 m.777doc.com 三七文档.

备案号:鲁ICP备2024069028号-1 客服联系 QQ:2149211541

×
保存成功