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11FIFO/***********************************************************************\***Module:fifoctlr_icmw1.vLastUpdate:07/14/00****Description:FIFOcontrollertoplevel.**Implementsa1020x4Read,255x16WriteFIFOwith**independentread/writeclocks.****ThefollowingVerilogcodeimplementsa1020x4Read,255x16Write**FIFOinaVirtexdevice.TheinputsareaReadClockandRead**Enable,aWriteClockandWriteEnable,WriteData,andaFIFO_gsr**signalasaninitialreset.TheoutputsareReadData,Full,Empty,**andtheFIFOcountoutputs,whichindicateroughlyhowfulltheFIFO**is.****Designer:NickCamilleri****Company:Xilinx,Inc.****Disclaimer:THESEDESIGNSAREPROVIDEDASISWITHNOWARRANTY**WHATSOEVERANDXILINXSPECIFICALLYDISCLAIMSANY**IMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFOR**APARTICULARPURPOSE,ORAGAINSTINFRINGEMENT.**THEYAREONLYINTENDEDTOBEUSEDBYXILINX**CUSTOMERS,ANDWITHINXILINXDEVICES.****Copyright(c)2000Xilinx,Inc.**Allrightsreserved***\***********************************************************************/`timescale1ns/10ps`defineDATA_WIDTHR3:0`defineDATA_WIDTHW15:0`defineADDR_WIDTH7:0`defineMINORADDR_WIDTH1:0`defineCARRY_WIDTH7:0modulefifoctlr_icmw1(read_clock_in,write_clock_in,read_enable_in,write_enable_in,fifo_gsr_in,write_data_in,read_data_out,full_out,empty_out,fifostatus_out);inputread_clock_in,write_clock_in;inputread_enable_in,write_enable_in;inputfifo_gsr_in;input[`DATA_WIDTHW]write_data_in;output[`DATA_WIDTHR]read_data_out;outputfull_out,empty_out;output[3:0]fifostatus_out;wireread_enable=read_enable_in;wirewrite_enable=write_enable_in;wirefifo_gsr=fifo_gsr_in;wire[`DATA_WIDTHW]write_data=write_data_in;wire[`DATA_WIDTHR]read_data;assignread_data_out=read_data;reg[7:0]fifostatus;assignfifostatus_out=fifostatus[7:4];regfull,empty;assignfull_out=full;assignempty_out=empty;reg[`ADDR_WIDTH]read_addr,write_addr;reg[`ADDR_WIDTH]write_addrgray,write_nextgray;reg[`ADDR_WIDTH]read_addrgray,read_nextgray,read_lastgray;reg[`MINORADDR_WIDTH]read_addr_minor;wire[`CARRY_WIDTH]ecomp,fcomp;wire[`CARRY_WIDTH]emuxcyo,fmuxcyo;wireread_allow,write_allow,read_allow_minor;wirefull_allow,empty_allow;wireemptyg,fullg;wire[`DATA_WIDTHR]gnd_bus='h0;wiregnd=0;wirepwr=1;/**********************************************************************\***Globalinputclockbuffersareinstantiantedforboththeread_clock**andthewrite_clock,toavoidskewproblems.***\**********************************************************************/BUFGPgclkread(.I(read_clock_in),.O(read_clock));BUFGPgclkwrite(.I(write_clock_in),.O(write_clock));/**********************************************************************\***BlockSelectRAMinstantiationforFIFO.Moduleis256x16,of**whichoneaddresslocationissacrificedfortheoverallspeedof**thedesign.NOTE:the4-bitreaddatawillcomeoutLSBtoMSB**relativetotheoriginal16-bitwordwritten.e.g.thefirst4-bit**nibblewillbeword[3:0],then[7:4],[11:8]andfinally[15:12].***\**********************************************************************/RAMB4_S4_S16bram1(.ADDRA({read_addr,read_addr_minor}),.ADDRB(write_addr),.DIA(gnd_bus),.DIB(write_data),.WEA(gnd),.WEB(pwr),.CLKA(read_clock),.CLKB(write_clock),.RSTA(gnd),.RSTB(gnd),.ENA(read_allow_minor),.ENB(write_allow),.DOA(read_data),.DOB());/************************************************************\***AllowflagsdeterminewhetherFIFOcontrollogiccan**operate.Ifread_enableisdrivenhigh,andtheFIFOis**notEmpty,thenReadsareallowed.Similarly,ifthe**write_enablesignalishigh,andtheFIFOisnotFull,**thenWritesareallowed.***\************************************************************/assignread_allow_minor=(read_enable&&!empty);assignread_allow=(read_allow_minor&&(read_addr_minor==2'b11));assignwrite_allow=(write_enable&&!full);assignfull_allow=(full||write_enable);assignempty_allow=(empty||(read_enable&&(read_addr_minor==2'b11)));/***********************************************************\***Emptyflagissetonfifo_gsr(initial),orwhengray**codecountersareequal,orwhenthespecialdecoding**logicistrue(seebelowforfull/emptydecoding).***\***********************************************************/always@(posedgeread_clockorposedgefifo_gsr)if(fifo_gsr)empty='b1;elseif(empty_allow)empty=emptyg;/***********************************************************\***Fullflagissetonfifo_gsr(initial,butitiscleared**onthefirstvalidwrite_clockedgeafterfifo_gsris**de-asserted),orwhenthespecialdecodinglogicis**true(seebelowforfull/emptydecoding).***\***********************************************************/always@(posedgewrite_clockorposedgefifo_gsr)if(fifo_gsr)full='b1;elseif(full_allow)full=fullg;/************************************************************\***GenerationofReadaddresspointers.Theprimaryoneis**binary(read_addr),andtheGray-codederivativesare**generatedviapipeliningthebinary-to-Gray-coderesult.**Theinitialvaluesareimportant,sothey'reinsequence.**Thereisaminoraddresscreatedfortheportwiththe**smallerdatawidth,whichinthiscaseisthereadport.****Grey-codeaddressesareusedsothattheregistered**FullandEmptyflagsarealwaysclean,andneverinan**unknownstateduetotheasynchonousre