dsp_fpga

RInterfacingXilinxFPGAstoTIDSPPlatformsUsingtheEMIFApplicationNoteXAPP753(v2.0.1)January29,2007InterfacingXilinxFPGAstoTIDSPPlatforms(v2.0.1)January29,2007XilinxisdisclosingthisSpecificationtoyousolelyforuseinthedevelopmentofdesignstooperateonXilinxFPGAs.Exceptasstatedherein,noneoftheSpecificationmaybecopied,reproduced,distributed,republished,downloaded,displayed,posted,ortransmittedinanyformorbyanymeansincluding,butnotlimitedto,electronic,mechanical,photocopying,recording,orotherwise,withoutthepriorwrittenconsentofXilinx.AnyunauthorizeduseofthisSpecificationmayviolatecopyrightlaws,trademarklaws,thelawsofprivacyandpublicity,andcommunicationsregulationsandstatutes.XilinxdoesnotassumeanyliabilityarisingoutoftheapplicationoruseoftheSpecification;nordoesXilinxconveyanylicenseunderitspatents,copyrights,oranyrightsofothers.YouareresponsibleforobtaininganyrightsyoumayrequireforyouruseorimplementationoftheSpecification.Xilinxreservestherighttomakechanges,atanytime,totheSpecificationasdeemeddesirableinthesolediscretionofXilinx.Xilinxassumesnoobligationtocorrectanyerrorscontainedhereinortoadviseyouofanycorrectionifsuchbemade.XilinxwillnotassumeanyliabilityfortheaccuracyorcorrectnessofanyengineeringortechnicalsupportorassistanceprovidedtoyouinconnectionwiththeSpecification.THESPECIFICATIONISPROVIDED“ASISWITHALLFAULTS,ANDTHEENTIRERISKASTOITSFUNCTIONANDIMPLEMENTATIONISWITHYOU.YOUACKNOWLEDGEANDAGREETHATYOUHAVENOTRELIEDONANYORALORWRITTENINFORMATIONORADVICE,WHETHERGIVENBYXILINX,ORITSAGENTSOREMPLOYEES.XILINXMAKESNOOTHERWARRANTIES,WHETHEREXPRESS,IMPLIED,ORSTATUTORY,REGARDINGTHESPECIFICATION,INCLUDINGANYWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,TITLE,ANDNONINFRINGEMENTOFTHIRD-PARTYRIGHTS.INNOEVENTWILLXILINXBELIABLEFORANYCONSEQUENTIAL,INDIRECT,EXEMPLARY,SPECIAL,ORINCIDENTALDAMAGES,INCLUDINGANYLOSTDATAANDLOSTPROFITS,ARISINGFROMORRELATINGTOYOURUSEOFTHESPECIFICATION,EVENIFYOUHAVEBEENADVISEDOFTHEPOSSIBILITYOFSUCHDAMAGES.THETOTALCUMULATIVELIABILITYOFXILINXINCONNECTIONWITHYOURUSEOFTHESPECIFICATION,WHETHERINCONTRACTORTORTOROTHERWISE,WILLINNOEVENTEXCEEDTHEAMOUNTOFFEESPAIDBYYOUTOXILINXHEREUNDERFORUSEOFTHESPECIFICATION.YOUACKNOWLEDGETHATTHEFEES,IFANY,REFLECTTHEALLOCATIONOFRISKSETFORTHINTHISAGREEMENTANDTHATXILINXWOULDNOTMAKEAVAILABLETHESPECIFICATIONTOYOUWITHOUTTHESELIMITATIONSOFLIABILITY.TheSpecificationisnotdesignedorintendedforuseinthedevelopmentofon-linecontrolequipmentinhazardousenvironmentsrequiringfail-safecontrols,suchasintheoperationofnuclearfacilities,aircraftnavigationorcommunicationssystems,airtrafficcontrol,lifesupport,orweaponssystems(“High-RiskApplications”).XilinxspecificallydisclaimsanyexpressorimpliedwarrantiesoffitnessforsuchHigh-RiskApplications.YourepresentthatuseoftheSpecificationinsuchHigh-RiskApplicationsisfullyatyourrisk.©2004–2007Xilinx,Inc.Allrightsreserved.XILINX,theXilinxlogo,andotherdesignatedbrandsincludedhereinaretrademarksofXilinx,Inc.Allothertrademarksarethepropertyoftheirrespectiveowners.RevisionHistoryThefollowingtableshowstherevisionhistoryforthisdocument.RDateVersionRevision02/17/041.0InitialXilinxrelease.03/31/041.1RevisedFigures,additions,andnewinformationonreferencedesign.05/06/041.2Revisedtitle,addedPlatform.06/15/052.0AddedVirtex-4implementations.Convertedtochapterformat.01/26/072.0.1Changedlinktoreferencedesigns.InterfacingXilinxFPGAstoTIDSPPlatforms(v2.0.1)January29,2007RevisionHistory.............................................................2Preface:AboutThisGuideGuideContents..............................................................5AdditionalResources........................................................5TypographicalConventions..................................................6Chapter1:EMIFOverviewEMIF........................................................................7EMIFSignals..............................................................7EMIFClocking...........................................................10Byte-LaneAlignment......................................................10EMIFRegisters...........................................................11EMIFControlRegisters....................................................12CEControlRegisters....................................................12CESecondaryControlRegisters...........................................13GlobalControlRegister.................................................13PeripheralDeviceTransfer(PDT)ControlRegister............................13BoardLevelParameters.....................................................14Chapter2:Virtex-IISeriesorSpartan-3FPGAtoEMIFDesignFPGADesign...............................................................15BlockRAM..............................................................15BlockRAMFIFO.........................................................17COREGeneratorTool.....................................................17TMSC64xtoFPGAInterfaceSignals.........................................17DesignExamples.............