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理工大学学士学位论文I摘要随着计算机在人们生活中重要性和不可或缺性的提高，为了更方便的为大众使用，发展计算机性能成为IT行业的热点，但计算机的内部结构极其复杂，为了便于研究便产生了模型计算机。本文完成了基于VHDL的8位模型计算机的设计与实现。文中首先阐述了8位模型计算机的原理，然后对其十个功能模块（算术逻辑运算单元，累加器，控制器，地址寄存器，程序计数器，数据寄存器，存储器，节拍发生器，时钟信号源，指令寄存器和指令译码器）进行了分析与设计。最后在QuartusII9.0环境下进行了仿真，完成了8位模型计算机的整体实现。本文综合了计算机组成原理和数字逻辑与系统设计的知识，设计的8位模型计算机能更方便的了解计算机内部构造和工作原理。整个系统的开发体现了在QuartusII软件平台上用VHDL设计数字控制系统的实用性。关键词：8位模型机；QuartusII；VHDL语言理工大学学士学位论文IIAbstractWiththeimprovementofimportanceandindispensabilityincomputerinpeople'slife,inordertousemoreconvenientlyforpublic,computerperformanceisbecomingahotintheITindustrydevelopment.buttheinternalstructureofthecomputerisverycomplicate,Computermodelsimplifiesthedifficultyoftheresearch.ThisarticlecompletedthedesignandimplementationofeightmodelcomputerbasedonVHDL.First,thisarticleexpoundstheprincipleofeightmodelcomputer,thendividesitinto10modules(arithmeticlogicunit,accumulator,controllers,addressregister,theprogramcounteranddataregisters,memory,beatgenerator,aclocksignal,instructionregisterandinstructiondecoder)andanalyseanddesigneachofthem.FinallyundertheenvironmentoftheQuartusII9.0simulation,completedoverallimplementationofthe8modelcomputer.TheanalysisanddesignoftheeightmodelcomputerintegratedtheknowledgeofcomputerconstituteprincipleandDigitallogicandsystemdesign.Thedesignoftheeightmodelcomputercanbemoreconvenienttounderstandinternalstructureandworkingprinciple.ThewholesystemdevelopmentmanifeststhepracticabilityofdesigningthenumericalcontrolsystemontheQuartusIIsoftwareplatformwithVHDL.Keywords:eightmodelcomputer;VHDLlanguage;QuartusII理工大学学士学位论文III目录1绪论......................................................................................................................................11.1本课题研究的目的....................................................................................................11.2本课题研究的背景及意义........................................................................................12基于VHDL编程的基础知识.............................................................................................42.1VHDL语言概述........................................................................................................42.2VHDL的设计流程....................................................................................................52.3有关QuartusII的介绍.............................................................................................62.4本课题基于QuartusII的设计流程..........................................................................83基于VHDL8位模型机的原理与设计...............................................................................93.1模型计算机的原理....................................................................................................93.2模型机的总体设计要求............................................................................................93.3模型机逻辑框图的设计..........................................................................................103.3模型机的指令系统设计..........................................................................................103.4模型机的指令执行流程设计..................................................................................113.5基于VHDL8位模型机各模块的设计与实现.......................................................123.5.1算术逻辑单元ALU模块..............................................................................123.5.2累加器模块....................................................................................................143.5.3控制器模块....................................................................................................183.5.4节拍发生器....................................................................................................213.5.5指令寄存器模块IR和指令译码器..............................................................243.5.6时钟产生器....................................................................................................283.5.7程序计数器模块............................................................................................303.5.8地址寄存器MAR..........................................................................................333.5.9存储器RAM..................................................................................................363.5.10数据寄存器DR............................................................................................384基于VHDL的8位模型计算机的实现...........................................................................424.1基于VHDL的微程序执行流程图.........................................................................424.28位模型机的顶层原理图设计...............................................................................43理工大学学士学位论文IV4.3基于VHDL的8位模型机工作流程.....................................................................444.4顶层VHDL源程序设计.........................................................................................454.4.1头文件cpu_defs的VHDL设计...................................................................454.4.2CPU的VHDL源程序设计..........................................................................464.58位模型机的整体实现....................................................................................