Spartan-6存储器控制器用户手册

Spartan-6FPGAMemoryControllerUserGuideUG388(v2.1)March4,2010Spartan-6FPGAMemoryController(v2.1)March4,2010Xilinxisdisclosingthisuserguide,manual,releasenote,and/orspecification(theDocumentation)toyousolelyforuseinthedevelopmentofdesignstooperatewithXilinxhardwaredevices.Youmaynotreproduce,distribute,republish,download,display,post,ortransmittheDocumentationinanyformorbyanymeansincluding,butnotlimitedto,electronic,mechanical,photocopying,recording,orotherwise,withoutthepriorwrittenconsentofXilinx.XilinxexpresslydisclaimsanyliabilityarisingoutofyouruseoftheDocumentation.Xilinxreservestheright,atitssolediscretion,tochangetheDocumentationwithoutnoticeatanytime.XilinxassumesnoobligationtocorrectanyerrorscontainedintheDocumentation,ortoadviseyouofanycorrectionsorupdates.XilinxexpresslydisclaimsanyliabilityinconnectionwithtechnicalsupportorassistancethatmaybeprovidedtoyouinconnectionwiththeInformation.THEDOCUMENTATIONISDISCLOSEDTOYOU“AS-IS”WITHNOWARRANTYOFANYKIND.XILINXMAKESNOOTHERWARRANTIES,WHETHEREXPRESS,IMPLIED,ORSTATUTORY,REGARDINGTHEDOCUMENTATION,INCLUDINGANYWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ORNONINFRINGEMENTOFTHIRD-PARTYRIGHTS.INNOEVENTWILLXILINXBELIABLEFORANYCONSEQUENTIAL,INDIRECT,EXEMPLARY,SPECIAL,ORINCIDENTALDAMAGES,INCLUDINGANYLOSSOFDATAORLOSTPROFITS,ARISINGFROMYOURUSEOFTHEDOCUMENTATION.©Copyright2009–2010Xilinx,Inc.XILINX,theXilinxlogo,Virtex,Spartan,ISE,andotherdesignatedbrandsincludedhereinaretrademarksofXilinxintheUnitedStatesandothercountries.PCI,PCIExpress,PCIe,andPCI-XaretrademarksofPCI-SIG.Allothertrademarksarethepropertyoftheirrespectiveowners.RevisionHistoryThefollowingtableshowstherevisionhistoryforthisdocument.DateVersionRevision05/28/091.0InitialXilinxrelease.08/18/091.1•RemovedreferencestoMCBper-bitdeskewcalibration.�Chapter1:�AddedXC6SLX75andXC6SLX75TdevicesandCPG196,CSG484,andFG(G)900packagestoTable1-2,page13.�Chapter2:�InFigure2-2,page18,changedConfiguration5to128-bitbidirectional.�AddednoteregardingboarddesignrequirementsunderTable2-9,page30.�Chapter3:�UpdatedfirstparagraphinSupportedMemoryDevices,page35.�AddednotetoClocking,page37.�AddedsubsectionAdditionalBoardDesignRequirements,page42.�Chapter4:�MovedNote1fromFigure4-1,page44tobelowthefigure.�AddedNote2aboutcalibrationlogic.�AppendixA:�UpdatedJEDECspecificationlinksinMemoryStandards,page63.UG388(v2.1)March4,2010�MovedChapter3,“GettingStarted,”andChapter6,“DebuggingMCBDesigns,”andtoUG416,Spartan-6FPGAMemoryInterfaceSolutionsUserGuide.�ChangedintroductioninAboutThisGuide,page7.�Chapter1:�RevisedNote1inTable1-1,page12torefertothedatasheetforspecificvalues.�AddedNote2toTable1-2,page13.�Chapter2:�InTable2-3,changedthedescriptionandvaluesoftheC_MC_CALIBRATION_MODEattributeonpage25.�Appendedtwosentencestoexception(a)onpage30.�Chapter3:�Replacedtextregardingthespeedofthecalibrationclock,calib_clk,onpage38.�Chapter4:�RephrasedNote1underFigure4-1,page44.�InthethirdparagraphaftertheNotesonpage44,removedthesentenceaboutcalibrationlogic.�AddednoteafterfirstparagraphofCalibration,page45.�RemovedportionofsentenceaboutcalibrationlogicinfirstparagraphofPhase2:DQSCentering,page46.�AddedparagraphaboveFigure4-13,page56.�Addednoteonpage59beforeTable4-5.01/05/102.0.1Reviseddocumenthyperlinks.03/04/102.1Chapter1:IntheFeaturesandBenefitssection,addedbulletforinputterminationautomaticcalibrationtosection.InTable1-1,addedparametersinDataRateMinimumcolumnandupdatedtablenote2.InTable1-2,revisedtablenote1.Chapter2:InTable2-2,added“THREEQUARTERS”asapossiblevaluefortheMemoryDriveStrengthattribute,andmodifiedthedescriptionforMemoryBurstLengthattribute,indicatingthatDDR3isalwayssetto8.IntheClock,Reset,andCalibrationSignalssection,addedcalibrationtotheheadingname,introductorytext,andcaptionofTable2-4.InTable2-4,changedthesignalnameBUFPLLtoBUFPLL_MCB,changedthesignalnamesys_rsttoasync_rst,andaddedsignalsmcb_drp_clkandcalib_done.IntheMemoryDeviceInterfacesection,modifieddescriptivetextrelatedtoRZGandZIOpins.AddedclarifyingtextinNote(page30)relatingtounusedpinsfromanactiveMCBrevertingtogeneral-purposeI/O.InTable2-9,modifieddescriptionsfortherzqandziosignals.Chapter3:InTable3-1,removedmemorydevicesMT41K128M8xx-25andMT41K256M4xx-25.IntheClockingsection,addedtextrelatedtoMIG/EDKgenerationofclockinginfrastructure.ClarifiedtextrelatedtolocationofexternallydrivenPLL.Revisedtextrelatedtocalibrationclock.InFigure3-3,changedsignalnamefromcalib_clktomcb_drp_clk.ChangedtheendofthefirstsentenceafterFigure3-3.Changedthefirstsentenceaboutthecalibrationrelatedclockonpage38.UnderFigure3-4,addedclarifyingtextrelatedtousingbank1MCBpinsasBPIpins.IntheAdditionalBoardDesignRequirementssectiononpage42,clarifiedrequirementsforpull-downresistorsontheRESET,CKE,andODTsignals.AddedSimultaneousSwitchingOutputConsiderationssection.Chapter4:InthePhase1:InputTerminationsection,addedclarifyingtextrelatedtoinputterminationoftheRZQandZIOpins.IntheAddressingsection,addedclarifyingtextrelatedtooffsettingthestar