H27UDG8VEM-(Rev0.2)

Thisdocumentisageneralproductdescriptionandissubjecttochangewithoutnotice.Hynixdoesnotassumeanyresponsibilityforuseofcircuitsdescribed.Nopatentlicensesareimplied.Rev0.2/APR.200911PreliminaryH27UDG8VEMSeries128Gbit(16Gx8bit)NANDFlash128GbNANDFlashH27UDG8VEMRev0.2/APR.200921PreliminaryH27UDG8VEMSeries128Gbit(16Gx8bit)NANDFlashDocumentTitle128Gbit(16Gx8bit)NANDFlashMemoryRevisionHistoryRevisionNo.HistoryDraftDateRemark0.0InitialDraft.FEB.9.2009Preliminary0.11)RemovingthePSLpinandrelatedmaterial-ModifiedFigures:1,2,3,31-ModifiedTables:1,2,5,8-ModifiedText:Section4.3FEB.18.2009Preliminary0.21)ModifiedtCBSYR-60us-70us-ModifiedPart:Table112)ModifiedStatusRegisterCoding-Modifiedtext:Section3.7,3.11and3.13-ModifiedPart:Table4,Table13,Table14,Figure9,Figure14,Figure15,Figure16,Figure17,Figure18,Figure19,Figure20,Fig-ure25andFigure26-DeletedPart:Table15Apr.6.2009PriliminaryRev0.2/APR.200931PreliminaryH27UDG8VEMSeries128Gbit(16Gx8bit)NANDFlashFEATURESSUMMARYHIGHDENSITYNANDFlashMEMORIES-CosteffectivesolutionsformassstorageapplicationsNANDINTERFACE-x8buswidth.-MultiplexedAddress/Data-Pin-outcompatibilityforalldensitiesSUPPLYVOLTAGE-3.3Vdevice:VCC=2.7V~3.6VMemoryCellArray-(4K+224)bytesx128pagesx16384blocksPAGESIZE-x8device:(4096+224spare)bytesBLOCKSIZE-x8device:(512K+28K)bytesPAGEREAD/PROGRAM-Randomaccess:60us(max.)-Sequentialaccess:25ns(min.)30ns(min.)forCacheOperation-Pageprogramtime:1000us(typ.)-Multi-Planepageprogramtime:1000us(typ.)COPYBACKPROGRAM-Fastpagecopywithoutexternalbuffer-Multi-Planecopy-backprogramCACHEPROGRAM-Internal(4K+224)bytesbuffertoimprovetheprogramthroughputCACHEREAD-AutomaticblockdownloadwithoutlatencytimeFASTBLOCKERASE-Blockerasetime:3ms(Typ.)-Multi-Planeblockerasetime(2block):3ms(Typ.)STATUSREGISTERELECTRONICSIGNATURE-1stcycle:ManufacturerCode-2ndcycle:DeviceCode-3rdcycle:InternalChipNumber,CellType,NumberofSimultaneouslyProgrammedPages,InterleavedProgram,WriteCache-4thcycle:Pagesize,Blocksize,Redundantareasize-5thcycle:PlaneNumber,ECCLevel-6thcycle:Technology(DesignRule),EDO,InterfaceMULTI-PLANEOPERATION-Multipleplaneoperationtoimprovetheprogram/read/erase/cacheread/cacheprogramthroughputCHIPENABLEDON'TCAREOPTION-SimpleinterfacewithmicrocontrollerHARDWAREDATAPROTECTION-Program/EraselockedduringPowertransitionsDATARETENTION-5KProgram/EraseCycles(with12bit/512byteECC)-10yearsdataretentionPACKAGE-VLGA(14x18x1.0),DualInterfaceDualInterface-Descriptions,includingdiagramsandtables,applytoeachindividualCE#Rev0.2/APR.200941PreliminaryH27UDG8VEMSeries128Gbit(16Gx8bit)NANDFlash1.SUMMARYDESCRIPTIONTheH27UDG8VEM(TBD)isa16384Gx8bitwithspare224Mx8bitcapacity.Thedeviceisofferedin3.3VVccCorePowerSupply,3.3VInput-OutputPowerSupply.ItsNANDcellprovidesthemostcost-effectivesolutionforthesolidstatemassstoragemarket.Thememoryisdividedintoblocksthatcanbeerasedindependentlysoitispossibletopreservevaliddatawhileolddataiserased.Thedevicecontains32768blocks,composedby128pagesconsistingintwoNANDstructuresof32seriesconnectedFlashcells.Everycellholdstwobits.Likeallother4KBpageNANDFlashdevices,aprogramoperationallowstowritethe4,320bytepageintypical1000(TBD)usandaneraseoperationcanbeperformedintypical3msona512K-byteblock.Inadditiontothis,thankstomulti-planearchitecture,itispossibletoprogram2pagesatime(onepereachplane)ortoerase2blocksatime(again,onepereachplane).Asaconsequence,multi-planearchitectureallowstimereduction.Datainthepagecanbereadoutat25nscycletimeperbyte.(30nsforcacheRead)TheI/Opinsserveastheportsforaddressanddatainput/outputaswellascommandinput.Thisinterfaceallowsareducedpincountandeasymigrationtowardsdifferentdensities,withoutanyrearrangementoffootprint.Commands,DataandAddressesaresynchronouslyintroducedusingCE,WE,ALEandCLEinputpin.Theon-chipProgram/EraseCon-trollerautomatesallread,programanderasefunctionsincludingpulserepetition,whererequired,andinternalverificationandmarginingofdata.ThemodifyoperationscanbelockedusingtheWPInput.TheoutputpinR/B(opendrainbuffer)signalsthestatusofthedeviceduringeachoperation.InasystemwithmultiplememoriestheR/Bpinscanbeconnectedalltogethertoprovideaglobalstatussignal.Eventhewrite-intensivesystemscantakeadvantageoftheH27UDG8VEM(TBD)extendedreliabilityof5Kprogram/erasecyclesbyprovidingECC(ErrorCorrectingCode)withrealtimemapping-outalgorithm.ThechipsupportsCEdon'tcarefunction.ThisfunctionallowsthedirectdownloadofthecodefromtheNANDFlashmemorydevicebyamicrocontroller,sincetheCEtransitionsdonotstopthereadoperation.Thecopy-backfunctionallowstheoptimizationofdefectiveblocksmanagement:whenapageprogramoperationfailsthedatacanbedirectlyprogrammedinanotherpageinsidethesamearraysectionwithoutthetimeconsumingserialdatainsertionphase.Thecacheprogramfeatureallowsthedatainsertioninthecacheregisterwhilethedataregisteriscopiedintotheflasharray.Thispipelinedprogramoperationimprovestheprogramthroughputwhenlongfilesarewritteninsidethememory.Acachereadfeatureisalsoimplemented.Thisfeatureallowstodramaticallyimprovereadthroughputwhenconsecutivepageshavetobestreamedout.ThisdeviceincludesalsoextraFeatureslik