高速FPGA PCB设计指南

AlteraCorporation1AN-315-1.1PreliminaryApplicationNoteGuidelinesforDesigningHigh-SpeedFPGAPCBsIntroductionOverthepastfiveyears,thedevelopmentoftrueanalogCMOSprocesseshasledtotheuseofhigh-speedanalogdevicesinthedigitalarena.Systemspeedsof150MHzandhigherhavebecomecommonfordigitallogic.Systemsthatwereconsideredhighendandhighspeedafewyearsagoarenowcheaplyandeasilyimplemented.However,thisintegrationoffastsystemspeedsbringswithitthechallengesofanalogsystemdesigntoadigitalworld.Thisdocumentisaguidelineforprintedcircuitboard(PCB)layoutsanddesignsassociatedwithhigh-speedsystems.“Highspeed”doesnotjustmeanfastercommunicationrates(e.g.,fasterthan1gigabitpersecond(Gbps)).Atransistor-transistorlogic(TTL)signalwitha600-psrisetimeisalsoconsideredahigh-speedsignal.ThisopensuptheentirePCBtocarefulandtargetedboardsimulationanddesign.Thedesignermustconsideranydiscontinuitiesontheboard.The“Time-DomainReflectometry”and“Discontinuity”sectionsexplainhowtoeliminatediscontinuitiesonaPCB.Somesourcesofdiscontinuitiesarevias,rightangledbends,andpassiveconnectors.The“Termination”sectionexplainsaboutterminationsforsignalsonPCBs.Theplacementandselectionofterminationresistorsarecriticalinordertoavoidreflections.Assystemsrequirehigherspeeds,theyusedifferentialsignalsinsteadofsingle-endedsignalsbecauseofbetternoisemarginsandimmunity.DifferentialsignalsrequirespecialattentionfromPCBdesignerswithregardstotracelayout.The“TraceLayout”sectionaddressesdifferentialtracesintermsoftracelayout.Crosstalk,whichcanadverselyaffectsingleendedanddifferentialsignalsalike,isalsoaddressedinthissection.Allthedense,high-speedswitching(i.e.,hundredsofI/Opinsswitchingatratesfasterthan500-psriseandfalltimes)producespowerfultransientchangesinpowersupplyvoltage.Thesetransientchangesoccurbecauseasignalswitchingathigherfrequencyconsumesaproportionallygreateramountofpowerthanasignalswitchingatalowerfrequency.Asaresult,adevicedoesnothaveastablepowerreferencethatbothanaloganddigitalcircuitscanderivetheirpowerfrom.Thisphenomenoniscalledsimultaneousswitchingnoise(SSN).The“DielectricMaterial”sectiondiscusseshowtoeliminatesomeoftheseSSNproblemsthroughcarefulboarddesign.February2004,ver.1.12AlteraCorporationPreliminaryGuidelinesforDesigningHigh-SpeedFPGAPCBsTime-DomainReflectometryThe“SimultaneousSwitchingNoise”and“Decoupling”sectionscoverpowersupplydecouplingandPCBlayerstackup.Thedocumentdiscusseshowtoselectthemethodandamountofdecouplingaswellasthetheorybehindcapacitivedecoupling.Thesesectionsalsopresentareallifeexampleoftroubleshootingadecouplingproblem.The“LayerStackup”sectiondiscusseslayerstackup.Itiscriticaltofollowthebestpracticesdescribedinthisdocumenttoensurethebestperformancefromyoursystem.ThecontentofthisdocumentisbasedontheresultsofAltera'sexperimentswithhigh-speedPCBs.ThesimulationsweredonewithHspice,ananalogcircuitsimulator.Ansoft2Dand3DfieldsolverswereusedtoextractRLGCparametersfordifferentstructures.SigritySpeed2000toolwasusedforSSNsimulation.ThisdocumentshouldbeusedinconjunctionwiththeboardlayoutexampleprovidedontheAlterawebsite(www.altera.com).YoucanalsocontactAlteraApplicationsforthisexample.TheboardlayoutexampleisasetofspecificguidelinesusedwhendesigningtheStratixGXdevelopmentkitboard.Itincludesschematics,aboardspecificlayoutguideline,andboardlayoutandstackupinformation.YoushouldalsousethecharacterizationreportfortheAlteraFPGAyouaredesigningforwiththisdocument.Thisdocumentwillassistwithdesignguidelinesrequiredfortheboarddesign,andthecharacterizationreportwillgiveapictureofthedeviceperformance.ContactAlteraApplicationsforfurtherassistanceorquestionswithregardstothisdocumentoranyotherissuesassociatedwithhigh-speedboarddesign.Time-DomainReflectometryTimedomainreflectometry(TDR)isawaytoobservediscontinuitiesonatransmissionpath.Thetimedomainreflectometersendsapulsethroughthetransmissionmedium.Reflectionsoccurwhenthepulseofenergyreacheseithertheendofthetransmissionpathoradiscontinuitywithinthetransmissionpath.Fromthesereflections,thedesignercandeterminethesizeandlocationofthediscontinuity.ManyexamplesinthishandbookuseTDR,andthissectionprovidesanunderstandingofTDR.Figure1showsaTDRvoltageplotforacablethatisnotconnectedtoaPCB.Themiddlelineisa50-Ωcableonemeterlong.AtPointA,apulsestarts(Zo=50Ω)andtransmitsthroughthecable,stoppingattheendofthetransmissionline(i.e.,PointB).Becausetheendofthetransmissionlineisopen,thereisinfiniteimpedance,ZLOAD=α.Therefore,thereflectioncoefficientattheloadisdeterminedwiththeequation:AlteraCorporation3PreliminaryTime-DomainReflectometryGuidelinesforDesigningHigh-SpeedFPGAPCBsReflectioncoefficient=(ZLOAD–Zo)/(ZLOAD+Zo)Reflectioncoefficientinthiscase=(α–50)/(α+50)=1Theentiresignalisreflected.AtPointB,theamplitudeofthesignaldoubles.SeeFigure1.Figure1.TDRVoltagePlotwithCableNotConnectedtoPCBIfthesamemeter-longcableisthenconnectedtoaPCBthroughanSMAconnector,theplotchanges.SeeFigure2.BecausetheSMAconnectorismorecapacitivethaninductiveinnature,itappearsasacapacitiveload,shownasadipintheTDRplot.50ΩCablePointBPointA4AlteraCorporationPreliminaryGuid