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1CPLD/FPGA1PLD274/544000/4500()()RSFFRSFFEDFFDFFETFFTFFEJKFFJKFFELatch27413774138741397414574154745957459774164741657424474747437374374CPLD/FPGA11=41=211PLDCPLD/FPGAI/OGALCPLD/FPGA1000CPLDFPGACPLD/FPGAI/O2Moore()Mealy()3PLDGALCPLDFPGAGALGAL16V8GAL20V8GAL22V10ATV750ATV2500AlteraCPLD/FPGAAPEXFLEXMAXACEX4I/O31LatticeAtmelGAL16V820V820V10ATV7502AlteraCPLD/FPGAMax7000FLEX10KEACE1KConfigDevices3FastMapGAL4ProtelGAL5AlteraMaxPlusIIQuartusIICPLD/FPGA6---VHDLVerlogVHDLVHDL(Library)(Package)(Entity)(Architecture)(Configuration)(Declarations)(Block)(Process)(SignalAssignments)(Procedure)(Function)(ComponentIstantiations)7FPGAExpressSynplifyPro8ModelSimCPLD/FPGA14(BDC)LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYtri_outISGENERIC(bus_size:integer:=8);PORT(data_in:INstd_logic_vector(bus_size-1DOWNTO0);oe_en:INstd_logic;data_out:OUTstd_logic_vector(bus_size-1DOWNTO0));ENDtri_out;ARCHITECTUREbehaveOFtri_outISBEGINdata_out=data_inWHENoe_en='1'ELSE(OTHERS='Z');ENDbehave;2PLDPCMPS2UARTPCIUSB11DMACPLDVHDL-CPLDLIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYair_ctrlISPort(clk,temp_high,temp_low:INstd_logic;heat,cool:OUTstd_logic);ENDair_ctrl;ARCHITECTUREbehaveOFair_ctrlISTYPEstate_typeIS(just_right,too_cold,too_hot);SIGNALstate:state_type;5BEGINPROCESSBEGINWAITONclkUNTILRISING_EDGE(clk);IFtemp_low='1'THENstate=too_cold;ELSIFtemp_high='1'THENstate=too_high;ELSEstate=just_right;ENDIF;CASEstateISWHENjust_right=heat='0';cool='0';WHENtoo_cool=heat='1';cool='0';WHENtoo_high=heat='0';cool='1';ENDCASE;ENDPROCESS;ENDbehave;1,1998/5,22000.83CPLD2002.34CPLD/FPGA612PCIVHDL-CPLDPCIVHDLMaxPlusIIEPM7064SLC84-57PLDCPLD442004-9-12004-10-17IspPAC11992Lattice(In-SystemProgrammability),.21,199911,Lattice(In-SystemProgrammabilityProgrammableAnalogCircuits)(EDA)(ispLSI)28(1)(2)(3)3ispPAC10ispPAC20isp30isp80isp814ispPACPACDesigner92004-10-17