APEX Ⅱ型可编程逻辑器件

®AlteraCorporation1APEXIIProgrammableLogicDeviceFamilyAugust2002,ver.3.0DataSheetDS-APEXII-3.0Features...■Programmablelogicdevice(PLD)manufacturedusinga0.15-µmall-layercopper-metalfabricationprocess(uptoeightlayersofmetal)–1-gigabitpersecond(Gbps)True-LVDSTM,LVPECL,pseudocurrentmodelogic(PCML),andHyperTransportTMinterface–Clock-datasynchronization(CDS)inTrue-LVDSinterfacetocorrectanyfixedclock-to-dataskew–EnablescommonnetworkingandcommunicationsbusI/OstandardssuchasRapidIOTM,CSIX,UtopiaIV,andPOS-PHYLevel4–Supportforhigh-speedexternalmemoryinterfaces,includingzerobusturnaround(ZBT),quaddatarate(QDR),anddoubledatarate(DDR)staticRAM(SRAM),andsingledatarate(SDR)andDDRsynchronousdynamicRAM(SDRAM)–30%to40%fasterdesignperformancethanAPEXTM20KEdevicesonaverage–Enhanced4,096-bitembeddedsystemblocks(ESBs)implementingfirst-infirst-out(FIFO)buffers,Dual-Port+RAM(bidirectionaldual-portRAM),andcontent-addressablememory(CAM)–High-performance,low-powercopperinterconnect–Fastparallelbyte-widesynchronousdeviceconfiguration–Look-uptable(LUT)logicavailableforregister-intensivefunctions■High-densityarchitecture–1,900,000to5,250,000maximumsystemgates(seeTable1)–Upto67,200logicelements(LEs)–Upto1,146,880RAMbitsthatcanbeusedwithoutreducingavailablelogic■Low-poweroperationdesign–1.5-Vsupplyvoltage–Copperinterconnectreducespowerconsumption–MultiVoltTMI/Osupportfor1.5-V,1.8-V,2.5-V,and3.3-Vinterfaces–ESBsofferprogrammablepower-savingmode2AlteraCorporationAPEXIIProgrammableLogicDeviceFamilyDataSheetNotestoTable1:(1)Eachdevicehas36inputchannelsand36outputchannels.(2)EP2A15andEP2A25deviceshave56inputand56outputchannels;EP2A40andEP2A70deviceshave88inputand88outputchannels.(3)PLL:phase-lockedloop.True-LVDSPLLsarededicatedtoimplementTrue-LVDSfunctionality.(4)TwointernaloutputsperPLLareavailable.Additionally,thedevicehasoneexternaloutputperPLLpair(twoexternaloutputsperdevice)....andMoreFeatures■I/Ofeatures–Upto380GbpsofI/Ocapability–1-GbpsTrue-LVDS,LVPECL,PCML,andHyperTransportsupporton36inputand36outputchannelsthatfeatureclocksynchronizationcircuitryandindependentclockmultiplicationandserialization/deserializationfactors–CommonnetworkingandcommunicationsbusI/OstandardssuchasRapidIO,CSIX,UtopiaIV,andPOS-PHYLevel4enabled–400-megabitspersecond(Mbps)Flexible-LVDSandHyperTransportsupportonupto88inputand88outputchannels(inputchannelsalsosupportLVPECL)–Supportforhigh-speedexternalmemories,includingZBT,QDR,andDDRSRAM,andSDRandDDRSDRAM–CompliantwithperipheralcomponentinterconnectSpecialInterestGroup(PCISIG)PCILocalBusSpecification,Revision2.2for3.3-Voperationat33or66MHzand32or64bits–Compliantwith133-MHzPCI-Xspecifications–SupportforotheradvancedI/Ostandards,includingAGP,CTT,SSTL-3andSSTL-2ClassIandII,GTL+,andHSTLClassIandII–SixdedicatedregistersineachI/Oelement(IOE):twoinputregisters,twooutputregisters,andtwooutput-enableregisters–Programmablebusholdfeature–Programmablepull-upresistoronI/OpinsavailableduringusermodeTable1.APEXIIDeviceFeaturesFeatureEP2A15EP2A25EP2A40EP2A70Maximumgates1,900,0002,750,0003,000,0005,250,000Typicalgates600,000900,0001,500,0003,000,000LEs16,64024,32038,40067,200RAMESBs104152160280MaximumRAMbits425,984622,592655,3601,146,880True-LVDSchannels36(1)36(1)36(1)36(1)Flexible-LVDSTMchannels(2)56568888True-LVDSPLLs(3)4444General-purposePLLoutputs(4)8888MaximumuserI/Opins4926127351,060AlteraCorporation3APEXIIProgrammableLogicDeviceFamilyDataSheet–Programmableoutputdrivefor3.3-VLVTTLat4mA,12mA,24mA,orI/Ostandardlevels–Programmableoutputslew-ratecontrolreducesswitchingnoise–Hot-socketingoperationsupported–Pull-upresistoronI/Opinsbeforeandduringconfiguration■Enhancedinternalmemorystructure–High-density4,096-bitESBs–Dual-Port+RAMwithbidirectionalreadandwriteports–Supportformanyothermemoryfunctions,includingCAM,FIFO,andROM–ESBpackingmodepartitionsoneESBintotwo2,048-bitblocks■Deviceconfiguration–Fastbyte-widesynchronousconfigurationminimizesin-circuitreconfigurationtime–Deviceconfigurationsupportsmultiplevoltages(either3.3Vand2.5Vor1.8V)■Flexibleclockmanagementcircuitrywitheightgeneral-purposePLLoutputs–Fourgeneral-purposePLLswithtwooutputsperPLL–Built-inlow-skewclocktree–Eightglobalclocksignals–ClockLockTMfeaturereducingclockdelayandskew–ClockBoostTMfeatureprovidingclockmultiplication(by1to160)anddivision(by1to256)–ClockShiftTMfeatureprovidingprogrammableclockphaseanddelayshiftingwithcoarse(90°,180°,or270°)andfine(0.5to1.0ns)resolution■Advancedinterconnectstructure–All-layercopperinterconnectforhighperformance–Four-levelhierarchicalFastTrack®interconnectstructureforfast,predictableinterconnectdelays–Dedicatedcarrychainthatimplementsarithmeticfunctionssuchasfastadders,counters,andcomparators(automaticallyusedbysoftwaretoolsandmegafunctions)–Dedicatedcascadechainthatimplementshigh-speed,high-fan-inlogicfunctions(automaticallyusedbysoftwaretoolsandmegafunctions)–InterleavedlocalinterconnectallowingoneLEtodrive29otherLEsthroughthefastlocalinterconnect■Advancedsoftwaresupport–Softwaredesignsupportandautomaticplace-and-routeprovidedbytheAlte