搜索
EDA课程设计报告设计（论文）题目：多功能数字时钟的设计学院名称：电子与信息工程学院专业：电子科学与技术班级：电科102姓名：感谢我吧学号哈哈小组成员：ok指导教师：王蔚日期：2013年12月18日一、简述·································································二、设计要求说明·························································2.1设计总体要求·····················································2.2设计基本要求·····················································2.3设计提高部分要求·················································三、系统设计·····························································3.1整体设计方案······················································3.2秒脉冲发生电路····················································3.3译码显示电路······················································3.4计时电路······················································3.5复位电路··························································四、功能模块电路设计······················································4.1秒脉冲发生电路模块···············································4.2整体时钟设计模块·················································五、系统调试·····························································5.1系统调试·························································5.11消抖电路调试·····················································5.12计时电路调试·····················································5.13秒产生电路调试····················································5.14整点报时电路调试···················································5.15数码显示电路调试·················································5.16时校时电路调试·················································5.17状态灯电路调试·················································5.2管脚分配·························································六、参考文献·····························································七、实验感想·····························································摘要：本次EDA课程设计利是在QuartusII软件平台上用verilog硬件语言来编程设计PLD电路，最终设计出一简单的数字时钟电路，并且将程序代码烧写到EDA试验箱进行验证。本次设计充分采用了软件编程中分层次、模块化的编程思想，同时也充分考虑到了硬件结构编程与纯软件编程的差异性，仿真与实际烧写相结合，逐步完善其逻辑、功能。本系统主要由时钟基本功能电路、闹钟电路、动态显示控制电路、分频电路，状态灯显示电路，按键电路组成，实现了时分秒的计时、闹钟报时，整点报时，调整时分等功能。关键字：数字时钟；模块化；分层思想；硬件结构Abstract:TheEDAcurriculumdesignbenefitisthesoftwareplatformonQuartusIIveriloghardwaredesignlanguageforprogrammingPLDcircuit,thefinaldesignofasimpledigitalclockcircuit,andtheEDAprogramcodeintothechamberforverification.Thefulluseofthesoftwareprogramdesignedhierarchically,modularprogrammingideas,butalsogivefullconsiderationtothestructureofprogrammingandhardwaredifferencespuresoftwareprogramming,simulationandactualprogrammingcombinedwiththegradualimprovementofitslogicfunction.Thesystemconsistsofabasicfunctionalcircuitclock,alarmcircuits,dynamicdisplaycontrolcircuit,dividercircuit,displaycircuitstatuslights,keycircuit,achievedwheneveryminutechronograph,alarmtime,thewholepointoftime,adjustinghoursandotherfunctions.Keyword:Digitalclock;modular;hierarchicalthinking;hardwarearchitecture一、简述在QuartusII软件平台上使用verilong硬件编程语言设计了简易的数字时钟，该时钟在控制电路的作用下具有保持、清零、快速校时、快速校分、整点报时、闹钟等功能。，可以完成一般的时钟任务。数字计时器的系统框图如下图所示:数字计时器的硬件电路框图如下图所示:数字时钟系统结构框图译码显示电路脉冲发生电路计时电路报时电路校时分电路清零电路闹钟电路复用开关电路段位码选择电路数码管显示蜂鸣器（报警彩铃）轻触按键（自动弹回式）控制电路（本次设计的内容）本次设计就是设计这一部分的数字逻辑控制电路二、设计要求说明（1）设计总体要求：利用QuartusII软件设计一个数字钟，对设计电路进行功能仿真，并下载到SmartSOPC实验系统中，可以完成00:00:00到23:59:59的计时功能，并在按键控制电路的作用下具有保持、清零、快速校时、快速校分、整点报时、闹钟等功能，做到能够创新的添加自己能够实现的功能。（2）设计基本要求1．进行正常的时、分、秒计时功能。2．分别由六个数码管显示时、分、秒的计时。3．有系统使能开关4．有系统清零开关5．有系统校分开关6.有系统校时开关（3）设计提高部分要求1．使时钟具有整点报时功能2．闹表设定功能3．自己添加其他功能（4）已经完成的设计完成了进行正常的时、分、秒计时功能，能够通过数码管正常显示时、分、秒的计时，能够实现闹钟的设定以及闹醒功能，同时支持整点报时。按键设计上由于试验箱上8个按键完全足够使用，不需要按键复用，大大简化了按键扫描电路的设计，具体分配如下K0是系统的清零开关K0=0正常工作，K0=1时钟清零K1是系统的使能开关K1=0正常工作，K1=1时钟保持不变K2是系统的校时开关K2=0正常工作，K2=1时钟进入校时K3是系统的闹钟设置开关K3=0正常工作，K3=1时钟进入闹钟设置K4是系统的时（单位）加按键K4=0正常工作，K4=1时钟时加一K5是系统的分（单位）加开关K5=0正常工作，K5=1时钟分加一三、系统设计3.1整体设计方案多功能数字计时器是由计时电路、译码显示电路、脉冲发生电路和控制电路等几部分基本电路组成的，其中控制电路按照设计要求可以由校时电路、清零电路、报时电路和闹钟设计电路等组成。多功能数字钟控制器的系统框图如下图所示：控制电路原则确定的思路：首先需要考虑到的是此次设计要实现的功能有：①正常的计时、保持、清零、校时、校分以及整点报时功能；②闹铃功能，从使用者的角度来看闹铃需要设定相应的校分、校时功能；其次需考虑控制电路的设计有以下一些要求：1.考虑到有8个按键，按键数量完全能够满足本系统设计要求，不采用按键复用技术，简化编程步骤，方便使用者的操作，不易出错具有便捷的特点2.按键的干扰，充分考虑完善按键消抖的过程，防止误操作3.闹钟设定模块、正常时钟模块的切换不影响时钟的正常计时；多功能数字钟控制器系统结构图译码显示电路脉冲发生电路计时电路报时电路校对电路清零电路闹钟电路3.2整体设计算法流程开启电源，进入工作状态脉冲输入，为系统各个模块提供时钟模式按键的判断模式的选择校时模式（正常模式）按键判断时+1分+1计时模式清零按键时分秒全部清零Y正常计时模式闹钟模式按键判断时+1分+1N保持按键计时停止3.3译码显示模块一般的显示分为两种，即静态显示与动态显示；所谓静态显示，即每一个数码管由单独的七段显示译码器驱动，如要显示N位字符，必须用N个七段显示译码器，这种现实方法极大地浪费了芯片的控制管脚。动态显示则是利用了数据选择器的分时复用功能，将任意多位数码管的显示驱动，由一个七段显示译码器来完成。这样即节省了器件及芯片管脚，又提高了元件的使用效率。在此次实验中，我们采用了动态显示的方法，利用八进制计数器分别实现对秒个位、秒开始模式判断处理按键，执行操作十位、分个位、分十位、时个位、时十位利用一个六进制计数器实现扫描，扫描到的显示管的位选信号为1同时相应段码信号同时传到七段显示。扫描频率设置为1KHz，这样躲过人眼的辨别范围，使得肉眼看上去与静态显示没有什么区别。译码显示结构图：CLK1ms8位时钟数据输入8位数码管显示模块Count=?分频扫描数据DISP位选选中某个数码管段选,显示具体是数据Count+1//分频扫描数码管3.4计时电路段选位选数码管显示模块计时电路用的是1hz的时钟信号输入，从秒的个位开始分别开始自加1，直到秒信号累计到六十，开始进位至分钟的个位，一次类推一直到小时的十位。分别采用模60至模24的计数方式，实现计时功能。计时电路结构图：正常计时开始清零按键是否被按下进入正常计时模式Sec=Sec+1NYSec=0Min=0Hour=0Sec=59?NMin=Min+1Min=59?Min=0NHour=Hour+1Hour=23?Hour=0NYYY3.5清零电路复位电路采用k0开关来控制，实现的功能则是，当该键被按下之后，就可以实现计时清零功能。清零电路结构图：具体的参见上计时电路中的流程框图3.5脉冲发生电路48MHZ脉冲信号1HZ1KHZ500HZ分频电路（时钟分频，为数码管，按键蜂鸣器等提供时钟信号）3.6校时校分流程校时按键被按下模式判断闹钟模式计时模式Hour=24?Hour=hour+1Hour=0Nhour=24?Nhour=nhour+1N