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2004.8.511.1ASICASICApplicationSpecificIntegratedCircuitsASIC*PLD*CPLD*FPGA*GateArray*StandardCellEDAASICCPLDFPGAASICASICASIC7080CPLDFPGACMOSCMOSOTPPLDCMOSASICASICISP2080JTAGJointTestActionGroupIEEE1149.1-1990BSTBST2JTAGJTAG1-1JTAG1JTAG2IC1-1JTAGHDLRTLFSMVHDLCADCATEDAIEEE-1076VHDLASIC1.21.2.1PLDPROMPLAPALFPLAGALEPLDEEPLDFPGAFPGA1.2.2**EPROMUVEPROM3UVCMOS*EEPROMEECMOSUVEPROMFLASHMEMORY*SRAMPALFPGAGALSRAMFPGA1.2.3CPLDFPGAHCPLD1.2.4*PLD*CPLD*FPGA42.1PLDPLD74PLD74PLDPLDASIC2.2PLDPLDPLDPLDPLDPLDPLDPLD•PROM•PALGAL•PLA2-1PLAPROMPALPLAPAL21PALHLPRVPAL10H8PAL16L8PAL16P8PAL16R8PAL20V8PAL16H8PAL1682.3CPLDPLDPLDCPLDComplexProgrammableLogicDevice2-1PLA5CPLDEPLDErasablePLD2-2ALTERACPLDCPLDCPLDALTERAATMELCYPRESSLATTICEXILINX2-12-2ALTERAATMELCPLDALTERA://www.atmel.comCYPRESS://www.latticesemi.comXILINX(MHz)250MHz250MHz250MHz250MHztpd(max)1.2nS1.2nS1.2nS1.2nSGLB106400313616001024106400313616001024I/O2020410812096CPLDI/OCPLDI/ODCPLDI/OPLDCPLDALTERAFLEX2-2EABEmbeddedArrayBlockLABLogicArrayBlockLELogicElementI/OIOCI/OElementEEPROMEEPROMSRAMEEPROMSRAMMAX5000MAX7000FLEX8000MAX9000FLEX10K60-375060-5K2.5K-16K6K-12K10K-100K(MHz)125MHz178.6MHz125MHz125MHz70MHztpd(max)10nS5.0nS8nS8nSGLB16-19232-256208-1296320-560576-499216-19232-256208-1500484-772720-539208416484-208168-216150-40662-2AlteraFLEX10KFLEXLEFLEXLE4LUTLookUpTable4LE2-32-3AlteraFLEX10KCPLDLELEDTJKRSLABLABCTRL14LELELAB8LELABLABLABLELABEABRAM/ROMFLEXLABEABLABEAB7CPLD3.1CPLD3CPLDFPGAPCI/O3-1CPLDI/OLED57DIP16LED340PIN16LED/24bitsDIP3-2I/O3-2CPLDRS-232CPLD3-2CPLD8CPLDCPLD3-1PLEDP01CPLD3IOP01P02P03P04P06P07P08P09CPLD0305060708091011IOP13P14P15P16P18P19P20P21CPLD1617181921222324IOP22P23P24P25P27P28P29P30CPLD2527282930353637IOP34P35P36P37P39P40P41P42CPLD3839474849505152IOP43P44P45P46P48P49P50P51CPLD2527282930353637IOP55P56P57P58P60P61P62P63CPLD5354585960616264IOP64P65P66P67P69P70P71P72CPLD6566676970717273IOP76P77P78P79P81P82P83P84CPLD78798081448483IOI12I31I54I73CPLD1243423.2I/OI/OLED57DIP3.2.1DIPDIP324CPLD3-2DIPCPLD01DIPS1S216LEDD1D16DIP3-3DIP93-2CPLD脚DIP输开关对应关S1-1S1-2S1-3S1-4S1-5S1-6S1-7S1-8CPLD0305060708091011S2-1S2-2S2-3S2-4S2-5S2-6S2-7S2-8CPLD3839474849505152S3-1S3-2S3-3S3-4S3-5S3-6S3-7S3-8CPLD25272829303536373.2.2LED16LEDCPLD3-3LEDCPLDCD401063-3CPLDLEDCPLD5354585960616264CPLD65666769707172733.2.3LED6LEDDP1DP6LEDCPLD3-4CPLDLEDDA1CPLD1617181921222324DA2CPLD25272829303536373-4DP2DIPS3103.2.4I/OSWP1SWP4SWP4CPLDSWP14013-5CPLDSWP1CPLD448483CD40106RCF1F2F11KHz1MHzF21Hz1KHzF1CPLD2F2CPLD423.2.511VHDL4.1VHDLVHDLVeryHighSpeedIntegratedCircuitHardwareDescriptionLanguage1983EDAVHDL1EDA2EDA34.2VHDLCPLD/FPGAVHDL/RTLVHDLCPLD4-1CPLD/FPGA12EDACPLDCPLD3EDA4CPLDCPLD124.3VHDLVHDLCPLDRTL4.3.1VHDLLIBRARYieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;ENTITYcounterISPORT(A,B,CLK:instd_logic;D:outstd_logic);END;ARCHITECTUREbehavOFcounterISSIGNALE:std_logic;BEGIN--------------------------------------------------E=AandB;--------------------------------------------------PROCESS(CLK)BEGINIFCLK’eventandCLK=’1’THEND=E;ENDIF;ENDPROCESS;END;4-2VHDL4-2VHDL,:1.C,,LIBRARYieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;2ENTITYISPORT(12:instd_logic;34:instd_logic_vector(7downto0);56:outstd_logic);END;inoutstd_logicndowntom383.ARCHITECTUREOFISSIGNAL123:std_logic;BEGIN12……END;behavSIGNAL13ARCHITECTUREBEGIN4-2D4.3.2VHDL19std_logic10XUZXUZ2std_logic_vector9signalx:std_logic_vector(3downto0);xx(3),x(2),x(1),x(0)3integersignaly:integerrange0to15;CONV_INTEGERy=CONV_INTEGER(x)4.RAMROMtypeinstrisarray(0to15)ofstd_logic_vector(7downto0);signalIRAM:instr;instr816IRAMIRAM168RAMROM4.3.31=signalx:std_logic_vector(3downto0);signaly,z:std_logic;y=x(3);x(3)=x(2);y=z;y=1;x=0010;2ANDORNOTNANDNORXORXNORy=not(x(1)nandx(2)orx(3));3/===/=4.&x(3downto2)=x(1)&x(0);144.3.44.3.5PROCESS(12…)BEGINENDPROCESS;PROCESSPROCESSCASE,Ifthenelseendif;Ifthenendif;If1thenelsif2thenelseendif;IfLOAD=‘0’thenQ=Q+1;elseQ=QLOAD;Endif;CASECaseisWhen1when2|3|…=--“|”whenothers=Endcase;caseOPiswhen“00”=Q=Q+1;When“01”|“10”=--OP0110Q=QLOAD;Whenothers=Q=“0000”;Endcase;4.3.6COMPONENTVHDLARCHITECTUREBEGINCOMPONENTROMRAM4.3.7VHDL--4.4VHDLVHDL15VHDL4.4.1F=A•B•CF=AandBandC;process(A,B,C)beginF=AandBandC;Endprocess;process(A,B,C)beginifA=’1’andB=’1’andC=’1’thenF=‘1’;ElseF=’0’;Endif;Endprocess;CASE4.4.2DD123D,D12Qprocess(RSTCLK)beginifRST=’1’thenQ=‘0’;ElsifCLK’eventandCLK=’1’then--Q=D;Endif;Endprocess;4.4.3Latch12,QDprocess(LED)beginifLE=’1’thenQ=D;Endif;Endprocess;164.4.4CPUREG8WRDREG_ADDRsignalREG_ADDR:std_logic_vector(1downto0);signalD:std_logic_vector(7downto0);typecom_regisarray(0to3)ofstd_logic_vector(7downto0);signalREG:com_reg;process(CLK)beginifCLK’eventandCLK=’1’thenifWR=’1’thenREG(CONV_INTEGER(REG_ADDR))=D;Endif;Endif;Endprocess;RAM4.4.5RAMRAMRAMRAMRAMRAMCPLDRAMAlteraLPM_RAM_DQRAMwedataRAMaddressqaddresslpm_widthqdatalpm_widthadaddressARCHI