asynchronous techniques for system-on-chip design

INVITEDPAPERAsynchronousTechniquesforSystem-on-ChipDesignDigitalcircuitdesignsthatarenotsensitivetodelaypromisetoallowoperationwithoutclocksforfuturesystems-on-a-chip.ByAlainJ.Martin,MemberIEEE,andMikaNystro¨m,MemberIEEEABSTRACT|SoCdesignwillrequireasynchronoustechniquesasthelargeparametervariationsacrossthechipwillmakeitimpossibletocontroldelaysinclocknetworksandotherglobalsignalsefficiently.Initially,SoCswillbegloballyasynchronousandlocallysynchronous(GALS).Butthecomplexityofthenumerousasynchronous/synchronousinterfacesrequiredinaGALSwilleventuallyleadtoentirelyasynchronoussolutions.Thispaperintroducesthemaindesignprinciples,methods,andbuildingblocksforasynchronousVLSIsystems,withanem-phasisoncommunicationandsynchronization.Asynchronouscircuitswiththeonlydelayassumptionofisochronicforksarecalledquasi-delay-insensitive(QDI).QDIisusedinthepaperasthebasisforasynchronouslogic.Thepaperdiscussesasyn-chronoushandshakeprotocolsforcommunicationandthenotionofvalidity/neutralitytests,andcompletiontree.Basicbuildingblocksforsequencing,storage,functionevaluation,andbusesaredescribed,andtwoalternativemethodsfortheimplementationofanarbitrarycomputationareexplained.Issuesofarbitration,andsynchronizationplayanimportantroleincomplexdistributedsystemsandespeciallyinGALS.Thetwomainasynchronous/synchronousinterfacesneededinGALSVonebasedonsynchronizer,theotheronstoppableclockVaredescribedandanalyzed.KEYWORDS|Arbiter;asynchronous;asynchronousbus;asynchronous/synchronousinterface;C-element;completiontree;dual-rail;globallyasynchronousandlocallysynchronous(GALS);half-buffer;handshakeprotocol;isochronicfork;metastability;passive–activebuffer;prechargehalf-buffer(PCHB);quasi-delay-insensitive(QDI);stoppableclock;synchronizerI.INTRODUCTIONItisnowgenerallyagreedthatthesizableverylargescaleintegration(VLSI)systems[systems-on-chip(SoCs)]ofthenanoscaleerawillnotoperateunderthecontrolofasingleclockandwillrequireasynchronoustechniques.Thelargeparametervariationsacrossachipwillmakeitprohibi-tivelyexpensivetocontroldelaysinclocksandotherglobalsignals.Also,issuesofmodularityandenergyconsumptionpleadinfavorofasynchronoussolutionsatthesystemlevel.Whetherthosefuturesystemswillbeentirelyasyn-chronous,aswepredict,orgloballyasynchronousandlocallysynchronous(GALS),asmoreconservativepracti-tionerswouldhaveit,weanticipatethattheuseofasyn-chronousmethodswillbeextensiveandlimitedonlybythetraditionaldesigners’relativelackoffamiliaritywiththeapproach.Fortunately,thepasttwodecadeshavewitnessedspectacularprogressindevelopingmethodsandprototypesforasynchronous(clockless)VLSI.Today,acompletecatalogueofmaturetechniquesandstandardcomponents,aswellassomecomputer-aideddesign(CAD)tools,areavailableforthedesignofcomplexasynchro-nousdigitalsystems.Thispaperintroducesthemaindesignprinciples,methods,andbuildingblocksforasynchronousVLSIsystems,withanemphasisoncommunicationandsynchro-nization.Suchsystemswillbeorganizedasdistributedsystemsonachipconsistingofalargecollectionofcom-ponentscommunicatingbymessageexchange.Therefore,thepaperplacesastrongemphasisonissuesrelatedtonetworkandcommunicationVissuesforwhichasynchro-noustechniquesareparticularlywell-suited.Ourhopeisthatafterreadingthispaper,thedesignerofanSoCshouldbefamiliarenoughwiththosetechniquesthatheorshewouldnolongerhesitatetousethem.EventhoseadeptsofGALSwhoareadamantnottoletasynchronypenetratefurtherthanthenetworkpartoftheirSoCmustrealizethatnetworkarchitecturesforSoCsarerapidlybecomingsocomplexastorequirethemobilizationofthecompletearmoryofasynchronoustechniques.ManuscriptreceivedSeptember14,2005;revisedMarch3,2006.ThisworkwassupportedinpartbytheDefenseAdvancedResearchProjectsAgency(DARPA).TheauthorsarewiththeDepartmentofComputerScience,CaliforniaInstituteofTechnology,Pasadena,CA91125USA(e-mail:[e-mail]).DigitalObjectIdentifier:10.1109/JPROC.2006.875789Vol.94,No.6,June2006|ProceedingsoftheIEEE10890018-9219/$20.00
2006IEEEThepaperisorganizedasfollows.Thesecondsectioncontainsabriefhistoryandthemaindefinitionsofthedifferentasynchronouslogicsaccordingtotheirtimingassumptions.SectionIIIintroducesthecomputationalmodelsandlanguagesusedinthispapertodescribeandconstructasynchronouscircuits.SectionIVintroducesthemostcommonasynchronouscommunicationprotocolsandthenotionofvalidity/neutralitytests.Basicbuildingblocksforsequencing,storage,andfunctionevaluationareintro-ducedinSectionV.SectionVIpresentstwoalternativemethodsfortheimplementationofanarbitrarycomputa-tion:syntax-directeddecompositionanddata-drivendecom-position.Thetwoapproachesdifferinhowaspecificationisdecomposedintopipelinestages.SectionVIIdescribesseveralimplementationsofbuses.SectionVIIIdealswithissuesofarbitration,andsynchronization.SectionIXpre-sentstheasynchronous/synchronousinterfacesneededinaGALSsystem.II.ABRIEFHISTORYANDAFEWDEFINITIONSThefieldofasynchronousdesignisbotholdandnew.The1952ILLIACandthe1962ILLIACIIattheUniversityofIllinoisaresaidtohavecontainedbothsynchro-nousandasynchronousparts[2].The1960PDP6fromDigitalEquipment(DEC)wasalsoasyn