SMT-18CMPCD

©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaSemiconductorManufacturingTechnologyMichaelQuirk&JulianSerda©October2001byPrenticeHallChapter18ChemicalMechanicalPlanarization©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaObjectivesAfterstudyingthematerialinthischapter,youwillbeableto:1.Describetheterminologyforplanarization.2.Listanddiscussthreetraditionaltypesofplanarization.3.Discusschemicalmechanicalplanarization(CMP),theissuesofwaferplanarityandtheadvantageofCMP.4.DescribetheslurryandpadforbothoxideandmetalCMP.5.DiscussCMPequipment,includingendpointdetectionandwafercarriers.6.Explainthepost-CMPcleanprocedure.7.ListanddescribesevendifferentCMPapplications.©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaSingleMetalLayerICwithTopographyp+Siliconsubstratep–EpilayerFieldOxiden+n+p+p+n-wellILDOxidePadOxideMetalNitrideTopsideGateoxideSidewalloxidePre-metaloxidePolyMetalPolyMetalFigure18.1©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaTerminologyforWaferPlanarizationTypeofPlanarizationDescriptionSmoothingStepheightcornersroundedandsidewallssloped,buttheheightisnotsignificantlyreduced.PartialPlanarizationSmoothingplusareductioninstepheightlocally.LocalPlanarizationCompletefillingofsmallergaps(1–10m)orlocalareaswithinadie.Thetotalstepheighttoflatareasacrossthewaferisnotsignificantlyreduced.GlobalPlanarizationAchieveslocalplanarizationplusasignificantreductioninthetotalstepheightacrosstheentirewafersurface.Thisisalsoreferredtoasuniformity.Table18.1©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaQualitativeDefinitionsofPlanarizatione)Globalplanarizationa)Noplanarizationb)Smoothingc)Partialplanarizationd)LocalplanarizationFigure18.2©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaMultilayerMetallizationwithChemicalMechanicalPlanarization(CMP)InterlayerdielectricSubquartermicronCMOScrosssectionPlanarizedlayersofoxideandtungstenSiO2SiO2SiO2WWWFigure18.3©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaWaferProcessFlowwithCMPImplantDiffusionTest/SortEtchPolishPhotoCompletedwaferUnpatternedwaferWaferstartThinFilmsWaferFabrication(front-end)UsedwithpermissionfromAdvancedMicroDevicesFigure18.4©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaMultilayerMetallizationwithNon-planarizedandPlanarizedSurfacesNon-planarizedICproductPlanarizedICproductMicrographscourtesyofIntegratedCircuitEngineeringPhoto18.1©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaTraditionalPlanarization•Etchback•GlassReflow•Spin-on-films©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaEtchbackPlanarizationSiO2TopographyafteretchbackResistorSOGSiO2PlanarizingmaterialUndesirabletopographyFigure18.5©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaBPSGReflowPlanarizationBPSGSmoothingeffectofreflowBPSGDepositedinterlayerdielectricFigure18.6©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaSpinOnfilmwithEtchbackILD-1ILD-2deposition3)ILD-1SOG1)ILD-1SOGafterbaking2)Figure18.7©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaChemicalMechanicalPlanarization•CMPPlanarity•AdvantagesofCMP•CMPMechanisms•CMPSlurryandPad•CMPEquipment•CMPClean•CMPEquipmentManufacturers©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaSchematicofChemicalMechanicalPlanarization(CMP)WaferWafercarrierRotatingplatenPolishingslurrySlurrydispenserPolishingpadDownforceFigure18.8©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaWaferMeasurementsforDegreeofPlanarizationSiO2SubstrateMinMaxSHpreMinMaxSHpostPost-polishmeasurementPre-polishmeasurementSiO2Figure18.9©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaAdvantagesofCMPTable18.2BenefitsRemarks1.PlanarizationAchievesglobalplanarization.2.PlanarizedifferentmaterialsWiderangeofwafersurfacescanbeplanarized.3.Planarizemulti-materialsurfacesUsefulforplanarizingmultiplematerialsduringthesamepolishstep.4.ReduceseveretopographyReducestopographytoallowforfabricationwithtighterdesignrulesandadditionalinterconnectionlevels.5.AlternativemethodofmetalpatterningProvidesanalternatemeansofpatterningmetal(e.g.,Damasceneprocess),eliminatingtheneedoftheplasmaetchingfordifficult-to-etchmetalsandalloys.6.ImprovedmetalstepcoverageImprovesmetalstepcoverageduetoreductionintopography.7.IncreasedICreliabilityContributestoincreasingICreliability,speedandyield(lowerdefectdensity)ofsub-0.5mdevicesandcircuits.8.ReducedefectsCMPisasubtractiveprocessandcanremovesurfacedefects.9.NohazardousgasesDoesnotusehazardousgasescommonindryetchprocess.©2001byPrenticeHallSemiconductorManufacturingTechnologybyMichaelQuirkandJulianSerdaDisadvantagesofC