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SpecificationsispGAL22V101•IN-SYSTEMPROGRAMMABLE™(5-VONLY)—4-WireSerialProgrammingInterface—Minimum10,000Program/EraseCycles—Built-inPull-DownonSDIPinEliminatesDiscreteResistoronBoard(ispGAL22V10COnly)•HIGHPERFORMANCEE2CMOS®TECHNOLOGY—7.5nsMaximumPropagationDelay—Fmax=111MHz—5nsMaximumfromClockInputtoDataOutput—UltraMOS®AdvancedCMOSTechnology•ACTIVEPULL-UPSONALLLOGICINPUTANDI/OPINS•COMPATIBLEWITHSTANDARD22V10DEVICES—FullyFunction/Fuse-Map/ParametricCompatiblewithBipolarandCMOS22V10Devices•E2CELLTECHNOLOGY—In-SystemProgrammableLogic—100%Tested/100%Yields—HighSpeedElectricalErasure(100ms)—20YearDataRetention•TENOUTPUTLOGICMACROCELLS—MaximumFlexibilityforComplexLogicDesigns•APPLICATIONSINCLUDE:—DMAControl—StateMachineControl—HighSpeedGraphicsProcessing—Software-DrivenHardwareConfiguration•ELECTRONICSIGNATUREFORIDENTIFICATIONDESCRIPTIONTheispGAL22V10,at7.5nsmaximumpropagationdelaytime,combinesahighperformanceCMOSprocesswithElectricallyErasable(E2)floatinggatetechnologytoprovidetheindustry'sfirstin-systemprogrammable22V10device.E2technologyof-fershighspeed(100ms)erasetimes,providingtheabilitytore-programorreconfigurethedevicequicklyandefficiently.ThegenericarchitectureprovidesmaximumdesignflexibilitybyallowingtheOutputLogicMacrocell(OLMC)tobeconfiguredbytheuser.TheispGAL22V10isfullyfunction/fusemap/parametriccompatiblewithstandardbipolarandCMOS22V10devices.ThestandardPLCCpackageprovidesthesamefunctionalpinoutasthestandard22V10PLCCpackagewithNo-ConnectpinsbeingusedfortheISPinterfacesignals.UniquetestcircuitryandreprogrammablecellsallowcompleteAC,DC,andfunctionaltestingduringmanufacture.Asaresult,LatticeSemiconductordelivers100%fieldprogrammabilityandfunctionalityofallGALproducts.Inaddition,10,000erase/writecyclesanddataretentioninexcessof20yearsarespecified.FUNCTIONALBLOCKDIAGRAMFEATURESPINCONFIGURATIONPROGRAMMABLEAND-ARRAY(132X44)I/O/QI/O/QI/O/QI/O/QI/O/QI/O/QI/O/QI/O/QI/O/QI/O/QSDOSDIMODESCLKI/CLKIIIIIIIIIIRESETPRESET810121416161412108OLMCOLMCOLMCOLMCOLMCOLMCOLMCOLMCOLMCOLMCPROGRAMMINGLOGICIispGAL22V10In-SystemProgrammableE2CMOSPLDGenericArrayLogic™Copyright©1997LatticeSemiconductorCorp.Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders.Thespecificationsandinformationhereinaresubjecttochangewithoutnotice.LATTICESEMICONDUCTORCORP.,5555NortheastMooreCt.,Hillsboro,Oregon97124,U.S.A.July1997Tel.(503)681-0118;1-888-ISP-PLDS;FAX(503)681-3037;)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP5.75.65041JL7-C01V22LAGpsiCCLPdaeL-8201V22LAGpsiCL7-KdaeL-82POSS01V22LAGpsiBJL7-CCLPdaeL-820177041JL01-C01V22LAGpsiCCLPdaeL-8201V22LAGpsiC-01LKdaeL-82POSS01V22LAGpsiBJL01-CCLPdaeL-8251018041JL51-C01V22LAGpsiCCLPdaeL-8201V22LAGpsiC-51LKdaeL-82POSS01V22LAGpsiBJL51-CCLPdaeL-82IndustrialGradeSpecifications)sn(dpT)sn(usT)sn(ocT)Am(ccI#gniredrOegakcaP51018561IJL51-C01V22LAGpsiCCLPdaeL-8201V22LAGpsiC-51LIKdaeL-82POSSPARTNUMBERDESCRIPTIONBlank=CommercialI=IndustrialGradePackagePowerL=LowPowerSpeed(ns)XXXXXXXXXXXXXDeviceName_J=PLCCK=SSOPispGAL22V10CispGAL22V10BSpecificationsispGAL22V103OUTPUTLOGICMACROCELL(OLMC)OUTPUTLOGICMACROCELLCONFIGURATIONSispGAL22V10OUTPUTLOGICMACROCELL(OLMC)EachoftheMacrocellsoftheispGAL22V10hastwoprimaryfunc-tionalmodes:registered,andcombinatorialI/O.Themodesandtheoutputpolarityaresetbytwobits(SOandS1),whicharenor-mallycontrolledbythelogiccompiler.Eachofthesetwoprimarymodes,andthebitsettingsrequiredtoenablethem,aredescribedbelowandonthefollowingpage.REGISTEREDInregisteredmodetheoutputpinassociatedwithanindividualOLMCisdrivenbytheQoutputofthatOLMC’sD-typeflip-flop.Logicpolarityoftheoutputsignalatthepinmaybeselectedbyspecifyingthattheoutputbufferdriveeithertrue(activehigh)orinverted(activelow).Outputtri-statecontrolisavailableasanin-dividualproduct-termforeachOLMC,andcanthereforebede-finedbyalogicequation.TheDflip-flop’s/QoutputisfedbackintotheANDarray,withboththetrueandcomplementofthefeedbackavailableasinputstotheANDarray.NOTE:Inregisteredmode,thefeedbackisfromthe/Qoutputoftheregister,andnotfromthepin;therefore,apindefinedasregisteredisanoutputonly,andcannotbeusedfordynamicI/O,ascanthecombinatorialpins.COMBINATORIALI/OIncombinatorialmodethepinassociatedwithanindividualOLMCisdrivenbytheoutputofthesumtermgate.Logicpolarityoftheoutputsignalatthepinmaybeselectedbyspecifyingthattheoutputbufferdriveeithertrue(activehigh)orinverted(activelow).Outputtri-statecontrolisavailableasanindividualproduct-termforeachoutput,andmaybeindividuallysetbythecompileraseither“on”(dedicatedoutput),“off”(dedicatedinput),or“product-termdriven”(dynamicI/O).FeedbackintotheANDarrayisfromthepinsideoftheoutputenablebuffer.Bothpolarities(trueandinverted)ofthepinaref