《基于Quartus II的FPGACPLD数字系统设计与应用》范例的源程序

2-28moduleadder_4(cout,sum,ina,inb,cin,clk);output[3:0]sum;outputcout;input[3:0]Ina,inb;//tempa，tempb中间变量声明inputcin,clk;reg[3:0]tempa,tempb,sum;regcout;regtempc;//tempc中间变量声明always@(posedgeclk)//alwaysclk上升沿触发begin//阻塞语句tempa=ina;tempb=inb;tempc=cin;endalways@(posedgeclk)//alwaysclk上升沿触发begin{cout,sum}=tempa+tempb+tempc;endendmodule2-40`timescale1ns/10psmoduleadder4_testbench;reg[3:0]ina,inb;regcin;regclk=0;wire[3:0]sum;wirecout;always#10clk=~clk;initialbeginina=0;repeat(20)#20ina=$random;//随机数ina产生endinitialbegininb=0;repeat(10)#40inb=$random;//随机数inb产生endinitialbegincin=0;repeat(2)#200cin={$random}%16;//随机数inc产生#200$stop；endadder4adder4_te(.clk(clk),.sum(sum),.cout(cout),.ina(ina),.inb(inb),.cin(cin));initialendmodule2-73LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYSEG_7ISPORT(SEG:INSTD_LOGIC_VECTOR(3DOWNTO0);//--四位二进制码输入Q3:OUTSTD_LOGIC_VECTOR(6DOWNTO0));//--输出LED七段码ENDSEG_7;ARCHITECTUREARTOFSEG_7ISBEGINPROCESS(SEG)BEGINCASESEGISWHEN0000=Q3=0000001;--0WHEN0001=Q3=1001111;--1WHEN0010=Q3=0010010;--2WHEN0011=Q3=0000110;--3WHEN0100=Q3=1001100;--4WHEN0101=Q3=0100100;--5WHEN0110=Q3=0100000;--6WHEN0111=Q3=0001111;--7WHEN1000=Q3=0000000;--8WHEN1001=Q3=0000100;--9WHENOTHERS=Q3=1111111;ENDCASE;ENDPROCESS;ENDART;3-1`timescale1ns/1nsmoduleDecoder2x4(A,B,EN,Z);inputA,B,EN;output[0:3]Z;wireAbar,Bbar;assign#1Abar=~A;//语句1assign#1Bbar=~B;//语句2assign#2Z[0]=~(Abar&Bbar&EN);//语句3assign#2Z[1]=~(Abar&B&EN);//语句4assign#2Z[2]=~(A&Bbar&EN);//语句5assign#2Z[3]=~(A&B&EN);//语句6endmodule3-3moduleFASeq(A,B,Cin,Sum,Cout);inputA,B,Cin;outputSum,Cout;regSum,Cout;regT1,T2,T3;always@(AorBorCin)beginSum=(A^B)^Cin;T1=A&Cin;T2=B&Cin;T3=A&B;Cout=(T1|T2)|T3;endendmodule3-4`timescale1ns/1nsmoduleTest(Pop,Pid);outputPop,Pid;regPop,Pid;initialbeginPop=0;//语句1Pid=0;//语句2Pop=#51;//语句3Pid=#31;//语句4Pop=#60;//语句5Pid=#20;//语句6endendmodule3-5ModuleFourBitFA(FA,FB,FCin,FSum,FCout);parameterSIZE=4;input[SIZE:1]FA,FB;output[SIZE:1]FSuminputFCin;inputFCout;wire[1:SIZE-1]FTemp;FAStrFA1(.A(FA[1]),.B(FB[1]),.Cin(FCin),.Sum(FSum[1]),.Cout(FTemp[1])),FA2(.A(FA[2]),.B(FB[2]),.Cin(FTemp[1]),.Sum(FSum[2]),.Cout(FTemp[2])),FA3(.A(FA[3]),.B(FB[3]),.Cin(FTemp[2]),.Sum(FSum[3]),.Cout(FTemp[3])),FA4(.A(FA[4]),.B(FB[4]),.Cin(FTemp[3]),.Sum(FSum[4]),.Cout(FCout));endmodule3.1beginArt=0;Art=1;end3.2initialbeginCbn=0;Cbn=1;end3.3reg[0:2]QState;initialbeginQState=3’b011;QState=3’b100;$display(“CurrentvalueofQ_Stateis”%b,QState);#5;//等待一定的时延。$display(“ThedelayedvalueofQ_Stateis”%,bQState);end例3.4beginareg=breg;creg=areg;//creg的值为breg的值。end例3.5fork#50r='h35;#100r='hE2;#150r='h00;#200r='hF7;#250-end_wave;//触发事件end_waveJoin例3.6case(select[1:2])result=0;2'b01:result=flaga;2'b0x:result=flagb;2'b0z:result=flaga?'bx:0;2'b10:result=flagb;2'bx0,result=flagb;2'bz0:result=flagb?'bx:0;default:result='bx;endcase例3.7case(sig):1'bz:$display(signalisfloating);1'bx:$display(signalisunknown);default:$display(signalis%b,sig);endcase例3.8reg[7:0]ir;casez(ir)8'b1???????:instruction1(ir);8'b01??????:instruction2(ir);8'b00010???:instruction3(ir);8'b000001??:instruction4(ir);endcase例3.9reg[7:0]r,mask;mask=8'bx0x0x0x0;casex(r^mask)8'b001100xx:stat1;8'b1100xx00:stat2;8'b00xx0011:stat3;8'bxx001100:stat4;;endcase例3.10begin:init_memreg[7:0]tempi;for(tempi=0;tempimemsize;tempi=tempi+1)memory[tempi]=0;end例3.11parametersize=8,longsize=16;reg[size:1]opa,opb;reg[longsize:1]result;begin:multintegerbindex;result=0;for(bindex=1;bindex=size;bindex=bindex+1)if(opb[bindex])result=result+(opa(bindex-1));end例3.12initialbeginareg=0;//初始化寄存器aregfor(index=0;indexsize;index=index+1)memory[index]=0;//初始化一个memoryend例3.13alwaysareg=~areg;例3.14always#half_periodareg=~areg;4-2（1）代码一：moduleand_2(y,a,b);outputy;inputa,b;and(y,a,b);endmodule（2）代码二：moduleand_2(y,a,b);outputy;inputa,b;regy;always@(a,b)begincase({a,b})2'b00:y=0;2'b01:y=0;2'b10:y=0;2'b11:y=1;default:y='bx;endcaseendendmodule4-6(1)代码一：moduleor_2(y,a,b);outputy;inputa,b;or(y,a,b);endmodule(2)代码二：moduleor_2(y,a,b);outputy;inputa,b;regy;always@(a,b)begincase({a,b})2'b00:y=0;2'b01:y=1;2'b10:y=1;2'b11:y=1;default:y='bx;endcaseendendmodule4-10(1)代码一：modulenotput(y,a);outputy;inputa;not(y,a);endmodule(2)代码二：modulenotput(y,a);outputy;inputa;regy;always@(a)begincase({a})1'b0:y=1;1'b1:y=0;default:y='bx;endcaseendendmodule4-14（1）代码一：modulenand_2(y,a,b);outputy;inputa,b;nand(y,a,b);endmodule（2）代码二：modulenand_2(y,a,b);outputy;inputa,b;regy;always@(a,b)begincase({a,b})2'b00:y=1;2'b01:y=1;2'b10:y=1;2'b11:y=0;default:y='bx;endcaseendendmodule4-18(1)代码一：modulenor_2(y,a,b);outputy;inputa,b;nor(y,a,b);endmodule(2)代码二：modulenor_2(y,a,b);outputy;inputa,b;regy;always@(a,b)begincase({a,b})2'b00:y=1;2'b01:y=0;2'b10:y=0;2'b11:y=0;default:y='bx;endcaseendendmodule4-22modulenora(y,a,b,c,d);outputy;inputa,b,c,d;assigny=~(a&b|c&d);endmodule4-26(1)代码一：modulexor_2(y,a,b);outputy;inputa,b;xor(y,a,b);endmodule(2)代码二：modulexor_2(y,a,b);outputy;inputa,b;regy;always@(a,b)begincase({a,b})2'b00:y=0;2'b01:y=1;2'b10:y=1;2'b11:y=0;defa