Cadence-AMS-Designer-Tutorial

TuftsUniversityCadenceAMS-DesignerTutorialWrittenbyMichaelTrakimasFebruary2007TableofContents1.Introduction…………………………………………………………….………….......32.InitialSetup…………………………………………………………………………....33.IdealDACDesignExample…………………………………………………………...44.SimulationwithAMS-Designer………………………………………………….…...75.AdditionalDocumentation………………………………..…….……………………1421.IntroductionThistutorialismeanttogivethereaderenoughinformationtobeginusingAMS-DesignerinCadence.ThetutorialwillgooversettinguptheAMSenvironment,andwillgooverthedesignofanidealDAC.Itwillalsogiveanoverviewoftheinterconnectmodules,whicharenecessarytoconnectanaloganddigitalblockstoeachother.ThetutorialistailoredforusebystudentsatTuftsUniversity,butshouldbeapplicabletoCadenceinstallationsatotherinstitutions.Morein-depthinformationcanbefoundinthedocumentationsuppliedbyCadence,whichislistedintheAdditionalDocumentationsectionofthistutorial.AMS-Designerisasimulationenvironmentwhichallowsthesimulationofmixed-signaldesigns.ThesimulatorusesSpectreandNC-Verilogtosimulatetheanaloganddigitalpartsrespectively.Interconnectmodulesareusedtotranslatesignalsbetweenanaloganddigitalportswhichareconnectedtogether.Anothermixed-signalsimulatoravailableinCadenceisSpectreVerilog.AMS-DesignerisrecommendedoverSpectreVerilogbecauseitcanhandleVerilogAMScode,andalsousesabetterwaveformviewer.SpectreVerilogusesthesamewaveformviewerasSpectre,whichisdesignedfordisplayinganalogdata.AMS-DesignerusesSimVisiontoplottheoutputwaveforms.SimVisionisabletoplotanaloganddigitaldatamuchclearerthantheSpectrewaveformviewer.ItisnecessarytonotethatAMS-Designerandtheothermixed-signalsimulatorsarestillfairlynewtools.Moreworkmustbedoneonthembeforetheycanbeusedaseasilyandreliablyasthesimulatorsthatarededicatedtoeitheranalogordigitalsimulation.Forthisreason,itisrecommendedthatmixed-signalsimulationisonlyusedwhennecessary.Itismoreappropriatetodesignseparateblocks,whichonlyincludedigitaloranalogparts.TheseblockscanbeverifiedusingthemoreestablishedsimulatorssuchasSpectreandVerilog-XL.Theindividualblockscanthenbeconnectedtogetheratthetop-level,andthebehaviorofthewholecircuitcanbeverifiedwithAMS-Designer.2.InitialSetupBeforeusingAMS-Designer,afilenamed‘hdl.var’shouldbecreatedinthedirectorywhichyoulaunchCadencefrom.Thisfileisnotabsolutelynecessary,butitwillsuppresswarningsandpreventsomeunwantedbehavior.Thefollowingcontentshouldbeincludedinyour‘hdl.var’file.softinclude$INSTALL_DIR/tools/inca/files/hdl.vardefineamsdefineNCVLOGOPTS-linedebugdefineVIEW_MAP($VIEW_MAP,.vs=shell)defineWORK//my_design_library_name//$INSTALL_DIRisthedirectorywhereCadencewasinstalled.AtTuftsUniversity,theinstallationdirectoryforthemixed-signalpartsofCadenceis‘/loc/packages/cadence/solaris/IUS54/’.Theline‘defineWORK…’isincludedtotellAMS-Designerwhichlibrarytosearchforfiles.Thislineshouldbeomittedifthe‘hdl.var’filewillbeusedformultipledesignsindifferentlibraries.Thefollowinglineshouldbeaddedtoyour‘cds.lib’file.SOFTINCLUDE$INSTALL_DIR/tools/inca/files/cds.lib33.IdealDACDesignExampleThefollowingexamplewilltakeyouthroughthestepsinordertodesignandsimulateanidealDACusingAMSdesigner.TheexampleassumesthatthereaderisfamiliarwiththeCadencedesignenvironment,aswellaswithmodelinginverilogandverilogA.Tobeginwith,createanewlibrarycalled‘AMS_Tutorial.’NextcreateanewverilogAcellviewcalled‘ideal_dac’andcopythefollowingcodeintoit.//VerilogAforMprLibTest,ideal_dac,veriloga`includeconstants.h`includediscipline.hmoduleideal_dac(in,agnd,out);input[10:0]in;inputagnd;outputout;electrical[10:0]in;electricalagnd;electricalout;parameterreallogic_thresh=2.5;parameterrealfull_scale=1.0;parameterrealtrise=1nfrom[0:inf);parameterrealtfall=1nfrom[0:inf);realcode,delta;realpow2[11:0];integeri;analogbegin@(initial_step)beginpow2[0]=1.0;for(i=1;i=11;i=i+1)pow2[i]=2.0*pow2[i-1];endcode=0.0;//for(i=0;i11;i=i+1)begingeneratej(10,0)beginif(V(in[j])logic_thresh)delta=0.0;elsedelta=pow2[j];code=code+delta;endif(V(in[10])logic_thresh)code=code-pow2[11];code=full_scale*code/pow2[10];V(out)+V(agnd)+transition(code,0,trise,tfall);endendmoduleAftersavingthisfile,makesuretocreateasymbolforthecellview.Nextcreateaverilogcellviewcalled‘dac_driver’andcopythefollowingcodeintoit.moduledac_driver(word_out);output[10:0]word_out;reg[10:0]word_out;initialbeginword_out=12'h000;#20480$finish;endalways#5word_out=word_out+1'b1;endmoduleAftersavingthisfile,makesuretocreateasymbolforthecellview.4TheDACdriverwillbeusedtosupplytheidealDACwithalinearsequenceofdigitalwords.TheidealDACreadsinthedigitaldataandoutputsthecorrespondinganalogvalues.Thissystemcontainsbothdigitalandanalogsignals,andthereforerequirestheuseofamixed-signalsimulator.InorderfortheDACdriver,whichiscompletelydigital,tobeabletotalktotheanalogidealDAC,interconnectelementsmustbeused.Interconnectelementsareusedtoconvertadigital(analog)signalintoananalog(digital)signal,sothatananalogportcanbeconnectedtoadigitalport.ThisisnecessarytoconnectthedigitaloutputoftheDACdrivertotheanaloginputoftheidealDAC.AMS-Designercanautomaticallyinsertinterconnectelements,b