chapter04solutions《现代逻辑设计》电子工业出版社答案-第4章

Exercise4.1InthisparticularcaseusingaK-maptosimplifytheproblemwillnotbeveryusefulsinceadjacentcellsinaK-mapvarybyonlyonebit,andbecausethisisaparityfunctioneveryadjacentcellwillbeopposites.Startingwiththetruthtableforthefunction:InputOutput00001000100010000111010000101101101011101000010011101011011011001110101110011111UsingBooleanalgebrathefunctioncanbeexpressedasfollows:f=A’B’C’D’+A’B’CD+A’BC’D+AB’C’D+A’BCD’+AB’CD’+ABC’D’+ABCD=A’B’(C’D’+CD)+A’B(C’D+CD’)+AB’(C’D+CD’)+AB(C’D’+CD)=(A’B’+AB)(C’D’+CD)+(A’B+AB’)(C’D+CD’)=[(A’B’+AB)(C’D’+CD)+(A’B+AB’)(C’D+CD’)]””=[[(A’B’+AB)(C’D’+CD)]’[(A’B+AB’)(C’D+CD’)]’]’”=[[(A’B’+AB)(C’D’+CD)]’[(A’B+AB’)(C’D+CD’)]’]’”=[[(A’B’+AB)’+(C’D’+CD)’][(A’B+AB’)’+(C’D+CD’)’]]’”=[[(A’B’)’(AB)’+(C’D’)’(CD)’][(A’B)’(AB’)’+(C’D)’(CD’)’]]’”=[[(A’B’)’(AB)’+(C’D’)’(CD)’]’+[(A’B)’(AB’)’+(C’D)’(CD’)’]’]”=[[(A’B’)’(AB)’]’[(C’D’)’(CD)’]’+[(A’B)’(AB’)’]’[(C’D)’(CD’)’]’]”=[[(A’B’)’(AB)’]’[(C’D’)’(CD)’]’’[(A’B)’(AB’)’]’[(C’D)’(CD’)’]’’]’Assumingthatbothinputsandtheircomplementsareavailable,thediagrambelowshowshowmanyNANDgatesarerequired:Sincetherearefourtoapackage,thiswilltake3packagestoimplement.GoingbacktotheBooleansimplification,andthensimplifyingtoXORgatesgivesthefollowingresult:f=(A’B’+AB)(C’D’+CD)+(A’B+AB’)(C’D+CD’)=(A⊕B)’(C⊕D)’+(A⊕B)(C⊕D)=(A’⊕B)(C⊕D)’+(A’⊕B)’(C⊕D)=(A’⊕B)⊕(C⊕D)WhichcanbeimplementedusingasinglepackageofXORgates.Exercise4.2Ineachofthepartsbelowtheprob4_2blockscanbeassumedtoimplementthefunctionZ=(AB+CD)’.(a)(b)(c)(d)Exercise4.3Exercise4.4Thetablebelowmatchesinputsandoutputstothecorrespondingpinnumbers:PINSignal2A3B4C5D13C614C515C416C317C218C119C0Exercise4.5Asisshownwiththemultilevelfunctionsgiveninthechapter,itisincrediblydifficulttoevenfactortheequationsintoamultilevelfunctionsthathaveatotalof8outputsfromthePLA,andonlytwooutputsthatuse4ANDgates.Thus,youcannotfitthesolutionentirelyinaP14H8PAL.Exercise4.6Themaindifferencebetweensolutions4.3and4.4isthatin4.3youhavefullyprogrammableORplane,whereasin4.4youhaveafullyprogrammableANDplan.TheadvantageoftheORplaneisthatyoucanutilizecommonproducttermsforeachfunction;however,thisleadstoORgateswith2#ofinputsfanin.InthecaseofthePAL,theadvantageisbeingabletohavesmallerfan-inORgates,andonly2*(#ofinputs)fan-inontheANDgates.TheadvantageofthePLAimplementationisthatbothofthesestrategiescanbecombinedinordertoreducethenumberofANDgatesandthenumberofORgates.However,aPLAisgenerallyslowerbecausetheprogrammableplanestendtoslowthecircuitdownabit.Exercise4.7(a)(b)(c)(d)Exercise4.8(a)Amultiplexerwithncontrolbitstakes2ninputs,andbasedonthebinaryvalueofthecontrolbitsoutputs,supposethisnumberisi,thei-thinputisconnectedtotheoutputbit.Ademultiplexertakesasingleinputandhas2noutputs.Basedonthebinaryvalueofthencontrolbits,itwillpasstheinputvalueintothei-thoutputbit.Adecoderisthesameasademultiplexerexceptthatingeneraltheinputbitisviewedmoreasanenablesignalinthiscase.(b)Thefunctionbelowimplementsa2:4demultiplexer.Exercise4.9Exercise4.10(a)(b)(c)(d)Exercise4.11ABCDXYZ0000000000100100100100011011010000101010100110011011110010000101001011101010010111011100011110110011101011111110X=A’BCD+AB’CD’+AB’CD+ABC’D+ABCD’+ABCDY=A’B’CD’+A’B’CD+A’BC’D+A’BCD’+AB’C’D’+AB’C’D+ABC’D’+ABCDZ=A’B’C’D+A’B’CD+A’BC’D’+A’BCD’+AB’C’D+AB’CD+ABC’D’+ABCD’Exercise4.12AssumingF’isalsoavailable:(a)Toimplementthisfunction,thiswouldtake5packages,4ofwhichwouldbe8:1multiplexersandthelastonewouldbea4:1multiplexer.(b)Thecomponentbelowimplementsa4:1multiplexer.Sinceeachcontrolsignalonlyneedstobeinvertedoncefortheentirechip,onlyonepackageofinvertersisneeded.A32:1multiplexercanbeimplementedusing10ofthiscomponent,and2:1multiplexer(wherethe2:1multiplexerusesthree2-inputNANDgates).Thetablebelowdemonstrateshowmanyofeachtypeofgateisrequired,andhowmanypackagesforeach.GateTypeNumberofGatesNumberofPackagesInverters612-inputNAND313-inputNAND40144-inputNAND105TOTAL5921Exercise4.13(a)(b)(c)Onlyfive2:1multiplexersareneededtoimplementthefunction:(d)Yesitispossibleasshowninpart(c).Exercise4.14(a)(b)(c)(d)Note:inordertosimplifythediagramasingleorgateisused.InthiscasethedotsconnectingoutputwiresshouldbeinterpretedasseparateconnectionstotheORgatesincethedrawingtooluseddoesnothaveanorgatewithsufficientfan-in.Whena23-inputORgateisnotavailable,usingahierarchyofsmallerORgateswillaccomplishthesamething.Exercise4.15Thisimplementationusesa2:4decodertoenableasetof4:16decoders.Thusthefirst16outputswillbeenabledwhenA’B’isasserted,thesecond16outputswhenA’Bandsoon.Exercise4.16Exercise4.17(a)Note:Duetothelimitationsofthesoftwarebeingused,thedotsconnectingwiresshouldbeconsideredseparateinputstotheORgate.InthiscasetheOR-gateisan8-inputORgate.(b)Usingthenaïveimplementationindiscretegates,thisfunctiontakesfour3-inputANDgatesandone4-inputORgate.Whichcomparedtothesinglepackageforthedecoderandsinglepackageforthe8-inputORgateseemsprettybadintermsofnumberofgatesandwiresrequired.However,bysimplifyingthefunctionfirst:f=A’B’D+A’BD+AC’D’+ACD’=A’(B’+B)D+A(C’+C)D’=A’D+AD’=A⊕DThiscanbeimplementedusingasinglediscretegatewhichhassignificantlylessfan-inthanth