79电子系统设计09_电子系统设计实例

19.19.29.39.421997¾C19.19.1114090112()1338.121(4060)20.23(4060)¾40900.248.1940901Pt10000—1000.5Rt=R0(1+At+Bt*t)RttR00AB58.1989C5189C5151:SPCE061A8ADC2DACJTAG68.12.178.1KEY1:0—9KEY2:0—9KEY3:./AD1PC/88.12.21CPUSPCE061A8ADC2DAC32IO32K2K98.12IOA0KEY1IOA1KEY2IOA2KEY33LED108.14SPY0030118.15128.16Pt1000HT9274100Pt1380Ω(:1—2mA)10138.17PCPCSPCE061ATTLPCRS232MAX23296005148.13.1PID‰Pout=Kp*e(t)+Ki*e(t)+Kd(e(t)–e(t-1))Pout(t-1)=Kp*(e(t)–e(t-1)+Kie(t)+Kd(e(t)–2*e(t-1)+e(t-2))e(t)e(t)=e(t)+e(t-1)+e(t-2)+…….+e(1)e(t)–e(t-1)158.1ƒƒƒ168.13.2178.13.3188.13.51280---1002340600.43500.20.54PIDP280198.1SPCE061AI/O1997SPCE061A¾C9.22189C51A/DSRAMD/A9.222FPGAI/O9.2239.2243.13.21VR1A1=1+RP1/R3A2=1+RP2/R59.2253.3AGC9.2263.4300Hz3.4KHz50Hz8K9.2273.5ADCADC8ADC08098KFPGA1M2.5V9.2289.23.6DACDAC08323.74kHz3.8LM3863.932KB622563.1037KHz50KHzLM567299.2309.2319.2329.2libraryieee;useieee.std_logic_1164.all;entitysram2isport(clk:instd_logic;clk2:instd_logic;contro:instd_logic;--1:2sram0:1srammode:instd_logic;--1:lufang0:workingclr:instd_logic;rec1:instd_logic;play1:instd_logic;rec2:instd_logic;play2:instd_logic;enter:instd_logic;outer:instd_logic;co:instd_logic;eoc:instd_logic;adclk:outstd_logic;--adstart:outstd_logic;aoe:outstd_logic;soe1:outstd_logic;--sram2scs1:outstd_logic;swe1:outstd_logic;soe2:outstd_logic;scs2:outstd_logic;swe2:outstd_logic;dcs:outstd_logic;cn:outstd_logic;encnt:outstd_logic;e:outstd_logic;o:outstd_logic);endsram2;architectureaofsram2isTypestatesis(s0,s1,s2,s3,s4,s5,s6,s7);signalcurrent_state,next_state:states:=s0;beginTM:process(clk,contro,clr)beginif((contro='0')or(clr='1'))thencurrent_state=s0;elsifclk'eventandclk='1'thencurrent_state=next_state;endif;endprocess;........339.25.15.220mv50mv100mv200mv300mv500mv1V1.5V120mv260mv500mv1V1.4V1.8V2.4V3.4V65.2554.63.63.43.415HZ50HZ105HZ303HZ1KHZ1.5KHZ2KHZ2.4KHZ3.5KHZ10KHZ50mv0.24V0.7V1.1V1.2V1.2V1.1V1.0V0.8V0.2V349.2[1].EDA.[2].().[3].().[4]ASIC.VHDL100.359.2369.2