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LiamDevlinCEOPlextekRFIDesigningX-bandPAsUsingSMTPlasticPackagedGaNTransistorsLiamDevlinIntroduction/Overview•WhyplasticpackagedSMT•Substratechoice•DiscretedevicedetailsandperformanceforPAdesignexample(5WPAoptimisedfor9.3to9.5GHzband)•RFdesignandsimulationofthePA•Fastdrainswitchingcircuitry•PArealisation•Measuredperformance•SummaryandConclusionsWhyPlasticPackagedSMT?•Wideacceptability•Simplifiedhandling•Easeofassembly•Reducedcomponentcost•Reducedproductcost•However:–AsRFfrequencyandpowerincreasestheuseofSMTpresentsanincreasingchallenge–Carefulelectricalandthermaldesignisessential–AssemblymustbeveryrepeatabletoprovideconsistentparttopartperformanceSubstrateSelection•Rogers4003:–Dielectricconstant,r=3.55–Tan=0.0027•8milthickness•1ozfinalmetallisationweight•SolidCufilledviasunderthetransistor•Plating:Immersionsilver•Mountedonaluminiumcarrier,whichcanbeattachedtoheatsinkTransistorDetails•5Wtransistorin3mmx3mmover-moldedplasticpackage•TGF2977-SMfromQorvo•Bias:32VVds,25mAIdsRepresentativePCBforDeviceEvaluationS-parameters–TGF2977•5devicesmeasuredatroomtemperatureTransistorGmaxVersusFrequencyTransistorLoad-PullData•OptimumimpedancesformaximumpoweroutdifferfromthoseformaximumPAE•Compromiseselectedduringload-pullmeasurements:–Attheload:12.24-j9.23–Atthesource:13.82-j44.1BasicRFDesignApproachBiasTeeDesign•Radialstubatendofhighimpedance(200µmwideline),advantages:–Effectsofparasiticinductance(aswithSMTgroundingcap)areremoved–RadialstubhasmodesteffectatlowfrequenciesallowingtheadditionofSMTcomponentsforlowfrequencystability–ProvideslowimpedanceatsecondharmonicBiasTeeDesign•S11lookingintobiasteeatFo:BiasTeeDesign•S11lookingintobiasteeat2.Fo:BiasTeeDesign-Gate•Addinglowfrequencystabilisationtogatebiaspoint:BiasTeeDesign-Drain•Addinglowfrequencystabilisationtodrainbiaspoint:DCBlock•Highquality0603capacitorselected(withadequatebreakdownvoltage)•CapacitorparasiticsandSMTpadsmodelled:DCBlock•Capacitorvalueselectedtominimisein-bandloss(C=8.2pF):InputDampingCircuit•Tokilllowfrequencygainbuthaveminimaleffectonin-bandgain:InputDampingCircuit•Simulatedperformance:RFSimulationSchematic(priortolayoutandEM)RFLayoutforEMSimulation•InputandoutputnetworkssimulatedinseparateEMfiles•FacilityforRFperformanceoptimisationaddedinPCBlayoutpackageRFSimulationSchematic(includingEMblocks)SmallSignalRFSimulatedPerformance(IncludingEM)SimulatedLoadMatchComparedtoTargetTargetloadZ=12.24Ω-j*9.23ΩSimulatedloadZ=11.83Ω-j*4.4ΩSimulatedSourceMatchComparedtoTargetTargetsourceZ=13.82Ω-j*44.1ΩSimulatedsourceZ=13.85Ω-j*67.16ΩDrainSwitchingCircuitDesign•NominaldraincurrentofthedevicesatP-3dB400mA•Pulseduration:500µsmaximum,10µsminimum•Maximumdrainvoltagedroopoverthepulse:1V•0/+3VCMOScontrolSwitchingCircuitSchematicRFCircuitGaNPAR1R2R3R4RcRaRbCbCaCcTr1Tr2Tr3Tr4C1C2C3C4+32V0/3vlogicRbleedCircuitSchematicNotes•Schematicnotes:–PARFcircuitrycontainedwithinbluebox–Operatesfromasinglesupplyrail–Tr4:PMOShighsideswitch–C1–C4:localstoragecapacitance–LogiclowonTr1gate•Tr1isturnedoff,baseofTr2isat40v,sogateofTr4ishigh&channelisnonconducting,sodrainvoltageofTr4isatground.–LogichighonTr1gate•Tr1isturnedon,pullsbaseofTr3toaround30v,turningitontopullchargefromTr4gateandhenceturnonTr4,raisingthedrainvoltagetorail.–CorrectlysettingR1&R2ensuresTr4Vgsdoesnotgobelow-20v–R3isacurrentlimitforTr3–MaxpowerdissipationinPMOSswitch~0.26W(17%ofmaxrating)SelectedComponents•Valuesoptimisedtoallowgoodperformancefrom20Vto40VVds:–PMOSswitch(Tr4):Si7415DN–NMOS(Tr1):BSS138(SOT-23)–PNP(Tr3):SMBT2907A(SOT-23)–NPN(Tr2):MMBTA06LT1G(SOT-23)–R1:680R(1206)–R2:2x680R–R3:10R–R4:10k–C1toC4:330uF50VPanasonicEEEFK1H331AQSummaryofDrainSwitchingDesign•Voltagedroopin500µs:0.65V•Rise-time:(includingdelayof40ns)~100ns•Fall-time:(includingdelayof100ns)~250ns(to5V)A-0.500.511.522.5Time/mSecs200uSecs/div00.20.40.60.81V010203040I(Q4-G)I(Q5-drain)Q1-GQ2-baseQ4-DQ4-GComponentPlacementAssembledPAThermalConsiderations•SimulatedIdsversusPout:ThermalConsiderations•DCpowerdissipationsfor32VVds,10%dutycycle,P-3dB:–At10%dutycycle:1.075W–CW:10.75W•Totaldevicepowerdissipations(DC*(1-PAE))atP-3dB,32VVds,10%dutycycle;assuming50%PAE:–At10%dutycycle:0.54W–CW:5.4W•ThermalresistanceofQFNpackagedependsonbothpackagesizeanddie:–Initialestimate:17ºC/W–Subsequentdatasheetvalue(@85°Cbase):oAt10%dutycycle:14.9ºC/WoCW:15.9ºC/WThermalConsiderationscont’d•EstimatedjunctiontemperatureatP-3dBforbaseoftransistorat85ºC:–At10%dutycycle:93ºC–CW:171ºC•Note:–Baseoftransistorwillbeatahighertemperaturethanambient–Ambienttotransistorbasethermalimpedancedependson:oPCB(type,substratethickness,metallisation,viatype)oAttachmentofPCBtocarrier/heat-sinkoHeat-sink(size/style)oAirflowoverheat-sinkThermalConsiderationsThermalConsiderationsThermalConsiderationsMeasuredPerformanceof5WPAandteststructuresBiasTeeTestStructure•DrainBiasTeemeasuredtosimulated•Measuredlossat9.4GHz=0.12dBDampingCircuit-TestStructure•DampingCircuitmeasuredtosimulatedMeasuredS-parameters,overtemp•Vds:32V•Id:25mAMeasuredversusModelledS-parametersV2•Vds:32V•Id:25mA•Tamb=25°C•Measured•Simu