基于FPGA 的 FFT算法实现

101InnovationDriveSanJose,CA95134:November2008Copyright©2008AlteraCorporation.Allrightsreserved.Altera,TheProgrammableSolutionsCompany,thestylizedAlteralogo,specificdevicedesignations,andallotherwordsandlogosthatareidentifiedastrademarksand/orservicemarksare,unlessnotedotherwise,thetrademarksandservicemarksofAlteraCorporationintheU.S.andothercountries.Allotherproductorservicenamesarethepropertyoftheirrespectiveholders.AlteraproductsareprotectedundernumerousU.S.andforeignpatentsandpendingap-plications,maskworkrights,andcopyrights.AlterawarrantsperformanceofitssemiconductorproductstocurrentspecificationsinaccordancewithAltera'sstandardwarranty,butreservestherighttomakechangestoanyproductsandservicesatanytimewithoutnotice.Alteraassumesnoresponsibilityorliabilityarisingoutoftheapplicationoruseofanyinformation,product,orservicedescribedhereinexceptasexpresslyagreedtoinwritingbyAlteraCorporation.Alteracustomersareadvisedtoobtainthelatestversionofdevicespecificationsbeforerelyingonanypublishedinformationandbeforeplacingordersforproductsorservices.UG-FFT-8.0©November2008AlteraCorporationFFTMegaCoreFunctionUserGuidePreliminaryContentsChapter1.AboutThisMegaCoreFunctionReleaseInformation.....................................................................1–1DeviceFamilySupport...................................................................1–1Features................................................................................1–2GeneralDescription.....................................................................1–3FixedTransformSizeArchitecture......................................................1–3VariableStreamingArchitecture........................................................1–3OpenCorePlusEvaluation.............................................................1–3DSPBuilderSupport..................................................................1–4Performance............................................................................1–4Chapter2.GettingStartedDesignFlow............................................................................2–1FFTWalkthrough.......................................................................2–2CreateaNewQuartusIIProject.........................................................2–2LaunchIPToolbench..................................................................2–3Step1:Parameterize...................................................................2–4Step2:SetUpSimulation..............................................................2–8Step3:Generate......................................................................2–9SimulatetheDesign....................................................................2–12SimulateintheMATLABSoftware.....................................................2–12FixedTransformArchitectures......................................................2–12VariableStreamingArchitecture.....................................................2–13SimulatewithIPFunctionalSimulationModels..........................................2–14SimulatinginThird-PartySimulationToolsUsingNativeLink.............................2–14CompiletheDesign.....................................................................2–15FixedTransformArchitecture.........................................................2–15VariableStreamingArchitecture.......................................................2–16ProgramaDevice......................................................................2–16SetUpLicensing.......................................................................2–16Chapter3.FunctionalDescriptionBuffered,Burst,&StreamingArchitectures.................................................3–1VariableStreamingArchitecture...........................................................3–2TheAvalonStreamingInterface...........................................................3–3OpenCorePlusTime-OutBehavior........................................................3–4FFTProcessorEngineArchitectures........................................................3–4Radix-22SingleDelayFeedbackArchitecture.............................................3–5Quad-OutputFFTEngineArchitecture..................................................3–5Single-OutputFFTEngineArchitecture..................................................3–6ivFFTMegaCoreFunctionUserGuide©November2008AlteraCorporationPreliminaryI/ODataFlowArchitectures..............................................................3–7Streaming............................................................................3–7StreamingFFTOperation............................................................3–7EnablingtheStreamingFFT..........................................................3–8VariableStreaming....................................................................3–9ChangetheBlockSize...............................................................3–9EnablingtheVariableStreamingFFT........