基于FPGA的视频采集系统的设计与实现

华中科技大学硕士学位论文基于FPGA的视频采集系统的设计与实现姓名：李立申请学位级别：硕士专业：模式识别与智能系统指导教师：桑农20060508IAlteraStratixFPGARAMRAMFPGARAMRAMPCBAlteraCycloneFPGA:EP1C6Q240ADIADV7183BADV7183BI2CI2CVerilogHDLNiosRAMADV7183BI2CNiosIIAbstractThisdissertationgivesdetailsonhowtoimprovethereal-timeimagetrackingsystem.AndproposeanddesignadigitalvideocapturingsystembasedonFPGAtoconvertanalogvideosignalsintodigitalvideosignals,whichcanbeusedasthedigitalvideoresourcetothereal-timeimagetrackingsystem.Thedesignofreal-timeimagetrackingsystembasedonuncooledstaringIRfocalplanearrayhasspacetobeimproved.TheStratixseriesFPGAEP1S10whichishigh-endFPGAseriesofAlteraCorporationwasusedbutnotfullyused.Twoexternaldual-portRAMswereusedinthedesignalthoughEP1S10haslarge-volumeOn-Chipmemorythatcanbeutilized.Thus,itdidnotonlywastetheresource,butalsomakeithardtoroutePCB.Soitiseasytodrawtheconclusionthatreplacingthedual-portRAMontheFPGA-boardwithFPGA’sOn-Chipmemorycannotonlysaveadual-portRAMtocutthecost,butalsoeasethePCBrouting.Thisdissertationanalyzesthefeasibilityoftheimprovementinaspectsofmemoryvolumeandtiming.Whendebuggingthereal-timeimagetrackingsystemboards,theIRfocalplanemustbeprovidedsothattherearedigitalvideoresourcesforthesystemtoprocess.SincetheIRfocalplaneisexpensive,thereisonlysequencescenetransmittertoprovidedigitalimageresourcesinthelabnow.ButthesequencescenetransmitterislackofflexibilityforthatitcanonlyprovidesequenceimagestoredinthePC.Soifwecandesignadigitalvideocapturingsystemwhichcanconvertanalogvideosignalsintodigitalvideosignalsforsubsequentimageprocessing,ithasseveraladvantages.Firstofall,itcanofferanotherimagesourcesbesidesIRfocalplaneandsequencescenetransmitter,secondly,itgivesmoreflexibleimageresource,andthirdly,itcanreducethecost.Thisdissertationgivesdetailsonhowthissystemisdesignedandrealized.ThesystemisbasedonEP1C6Q240whichisCycloneseriesofAlteraCorporationandADV7183BwhichisavideodecoderofIIIADICorporation.I2CbusisrequiredtocontroltheADV7183B.Inthissystem,theI2Cbusfunctionisrealizedintwoways:VerilogHDLandNiosIIwhichisaverypopularsoft-core,moreover,theconceptIPCoreisfirstintroducedintheNiosIIsystem.Thesetwomethodshavebeencomparedbasedontheresult.Inthispaper,Idiscussindetailswhatthewatch-dogisandhowthewatch-dogcircuitisdesignedaswell.Meanwhile,Iintroduceanewdebuggingmethod,usingEmbeddedLogicAnalyzer(ELA)-SignalTapIIinsteadoftheexpensiveLogicAnalyzer.Ialsoexplainwhattheanaloganddigitalvideosare.Thisdissertationissummedupinafewwordsandseveralimprovementshavebeenproposedforthefutureresearch.Keywords:FPGAOn-ChipMemoryADV7183BVideoI2CNios()111.1FPGA/CPLDDSPCPU3FPGA/CPLDFPGA/CPLDFPGA/CPLDFPGAFPGA1.2FPGA1.2.1ASICASICASICASIC[1,2]PROM2EPROME2PROMPALGALCPLDFPGAFPGA/CPLDFPGACPUDSPFPGASOPCSystemOnProgrammableChip1.2.2PAL/GALCPLDFPGA31PAL/GALPALProgrammableArrayLogic;GALGenericArrayLogicPAL/GALE2CMOSPAL/GALCPLDFPGAGALGAL74GALGAL20GALGALLattice2CPLD3CPLDComplexProgrammableLogicDeviceCPLDPALGALE2CMOSFlashI/OCPLDPALGALCPLDAlteraLatticeXilinx3FPGAFPGAFieldProgrammableGateArrayFPGACPLDSRAMFlashAnti-FuseFPGAFPGA/RAMFPGAXilinxAlteraLatticeActelAtmel1.3FPGARAMRAMALTERACycloneFPGAEP1C6Q240ADIADV7183B4SignalTapADV7183BI2CNiosI2CHDLI2CFPGAIP1.4FPGASignaltapADV7183BI2CVerilogHDLI2CNiosNiosI2CI2CFPGAIPFPGAIPIP522.1“”FPGADSP[3-6]2.1RAMTMS320C6414FLASHRAMDACEP1S10F672EPROMPAL/D2.15V5V/3.3VFPGAFPGARAMDSPFPGAFPGARAMPAL/DDACPAL/DFPGADSP2.26DSPFPGARAM2.2FPGADSPFPGARAMDSPRAMDSPDSP2.3FPGADSP2.3FPGAFPGADSPFPGADSPFPGAFPGAI/ODSPINTxTMS320C6414FPGADSP7FPGA3BGAEP1S10F672RAMIDT70V639PCB3BGAFPGARAMRAMALTERAstratixFPGAEP1S10RAM920,448bits320*240*16bit1,228,800bitsEP1S10RAMRAMEP1S10RAMDSPDSPRAM2.2FPGARAM2.2.1AlteraFPGARAMStratixStratixStratixGXFPGA3RAM512bitM512,4kbitM4K,512kbitM-RAM3RAM[7]AlteraFPGACycloneStratixFPGARAMRAMRAMRAM2.4832Word(s)RAMBlockType:AUTOdata[7..0]address[4..0]wrenclockq[7..0]altsyncram1instdata[7..0]addr[4..0]wrenclockq[7..0]2.4FPGARAM2.2.2RAMRAMFPGALEFPGARAMRAMRAMRAMRAMRAMFIFOROM2.5RAMinclockoutclockinclockenoutclockeninaclroutaclr92.5RAM2.6RAMRAMRAMPseudoDualPortRAM2.6RAM2.7RAMABwren2.7RAMAlteraFPGARAMRAM10M4KM-RAMM512RAMRAMFIFORAMRAMM512M4KRAMFPGAROMM-RAMROM2.2.3RAMRAM2.2.4RAMRAMRAMUnknownM512M4KOldUnknownRAMMegaWiardRAM2.8112.8M512M4KRAMM-RAMFIFOFIFOFIFORAM2.3EP1S10[8]94M512RAM(32*18bits)60M4KRAM(128*36bits),1M-RAM(4K*144bits)614400bitsEP1S10RAMRAM3RAMRAMM-RAMM-RAM599824bits1/31/3DSPDSP33RAM12DSP[9,10]TMS320C6414100MHz0.01us1/3Tread=320*240*0.01*2/3=512us=0.512msFPGARAM6.875M0.148us1/38032064us1/3Twrite≈64*80=5120us=5.12msRAMRAM3201/31/38080DSPFPGAt=80*0.148=11.84us11.84usDSPn=11.840.01*2=5921/380*320=25,600DSPFPGAFPGA1/3DSPFPGAFPGADSP2.4QuartusaltsyncramRAMSimpledual-portmode,RAM1616M-RAM15DSPEMIFB100MHz2.913VCCDSP_CLKININPUT30000Word(s)RAMBlockType:M-RAMdata[15..0]wraddress[14..0]wrenrdaddress[14..0]wrclockrdclockq[15..0]altsyncram0inst8write_fram_data[15..0]write_fram_addr[14..0]write_fram_wrpixclktodsp_data[15..0]dsp_addr[14..0]2.9RAM3DSPDSP1/3DSP2.10irq11/3irq21/3DSPirq11/3DSP1/3VCCpixclkINPUTVCCdata_in[15..0]INPUTVCCline_enINPUTVCCfield_enINPUTirq1OUTPUTirq2