18MIPI-DSI-Essential(MIPI协议详细介绍)

MIPIDSIEssentialTableofContents■MIPIDSIOverview■PHYLayer▲D-PHYArchitecture▲GlobalOperation■LaneManagementLayer■DSIProtocolLayer2/59MIPIDSIOverview■SerialInterface▲LowPinCount▲ReducedPowerConsumption■2TypesofDataSignaling▲HighSpeedDataTransmission-500Mbps/Lane,differentialsignaling▲LowPowerDataTransmission-10Mbps,singleendedsignaling,lane0only■Lane-Scalable,upto4datalanes■PacketBasedDataTransmission▲DSIProtocolhasECC,CRCcapability-robustdatatransmission▲ProtocolSupportMultipledisplays(upto4)■SupportAllLegacyParallelInterfaceFunctionality▲MIPIDSICommandMode-MIPIDBIInterface(I-80Interface)▲MIPIDSIVideoMode-MIPIDPIInterface(RGBInterface)3/59MIPIDSIInterfacePhysicalArchitectureDSITransmitterDSIReceiverHostDevice,e.g.anApplicationProcessororBasebandProcessorcontainingDSITransmitterPeripheral,e.g.aDisplaycontainingtheDSIreceiverDataN+DataN-Clock+Clock-Data0+Data0-NDataLaneswhereNmaybe1,2,3,or4DataN+DataN-Clock+Clock-Data0+Data0-Bi-directionalHighSpeedDataLinks■1ClockLane,unidirectional■1to4DataLanes■Lane0isbidirectionalforLPdataoutputtransmissionofthedriverIC4/59MIPIDSIFunctionalLayersTransmitterSide8-bits8-bitsLowLevelProtocolDataControlDataControlAdd(TX)/Extract(RX)lowlevelprotocol,synchronization,ECC,CRCpacketheadersandfooters.LowLevelProtocolDataControlDataControlN*8-bitsTX:Distributedatato1,2,3or4lanesRX:Assemblydatafrom1,2,3or4toonebytestream8-bits8-bitsLaneManagementLayerLaneManagementLayerReceiverSidePHYLayerData3ControlPHYLayerControlPixeltoBytePackingFormatsDataControlPixelControlPack/UnpackPixelsorCommandsfrom/toByteStreamBytetoPixelUnpackingFormatsDataControlPixelControlApplicationPixelControlApplicationPixelControlEncodeandInterpretatData/Commands16-,18-or24-bitPixelsData2Data1Data0N*8-bitsData1Data3Data3Data0HighSpeedUnidirectionalClockLane0-HighSpeedbidirectionalDataLane1-HighSpeedUnidirectionalDataLane2-HighSpeedUnidirectionalDataLane3-HighSpeedUnidirectionalDataPhysicalTransmission/ReceptionSerializer/DeserializerByteClockGeneration/Recovery(DDR)perMIPID-PHYSpec5/59VideoModeDisplayDisplayDriverHostProcessorDisplayPanelLCDDisplayBusInterfaceBusInterfaceColorFrameBufferDisplayRefreshTimingControlUpdateFrameBuffer6/59CommandModeDisplayHostProcessorDisplayPanelLCDDisplayBusInterfaceColorFrameBufferImageUpdateDataCommands&ImageUpdateDataBusInterfaceDisplayController7/59PHYLayerD-PHYArchitecturePHYLaneConfiguration■MinimumConfiguration▲Atleast1ClockLane,1DataLane■Reverse-directiontrafficuseslane0only▲Lane1,2,3(ifpresent)areunidirectional■Lanenumberfixedatdesign/manufacture(Modulelevel)▲Nodynamiclaneconfigurationbyhostprocessor.9/59D-PHYLaneModule(1/2)■TransmissiondataUnit▲Onebyte■LaneModulemaycontain▲HS-TX,HS-RX,orboth■IfLPmodeisusedatcommandmodeconfiguration,bothhostandperipheralmustincludeLPRxandLPTx▲AlsoCDneededifbi-directionalinuse■TheLP-CDshallcheckforcontentionatleastoncebeforedrivinganewstateontheline■MasterandaSlaveconcept10/59D-PHYLaneModule(2/2)LowpowertransmitterHighspeedreceiverLowpowerreceiverContention(=“collision”)detectionHighspeedtransmitter11/59LeastPHYLaneConfiguration-DetailedViewDatalane0CLKlane*Bi-directionalbutnotHSreverse*LPforbi-directional*uni-directional*LPforminimumtransitioncontrol12/59D-PHYSignalLevel■2TypesofSignalLevel▲HSDT▲LPDTLPVOH-typ1.2V,1.1V~1.3VHSdiff-typ200mv,140mv~270mvHScomm-typ200mv,150mv~250mvLPVOH-typ0V,-50mV~50mVLPVIL:550mVLPVIH-typ1.2v0.88V~1.35V13/59HSMode-TransmitterReceiverStructure■HSDataTransmission▲WhileHSDTisactive,TerminationRisenabledR-term(ZID):100OhmTransmittersideReceiversidePCB,Conn,FPCB0V400mV300mV100mV14/59HSMode-SignalingDetailedView300mv100mv200mv100mv200mvVdiff=|VOD|■Vdiff200mV,Vcm200mVTypCondition15/59HSMode-ClockTransmission■HSClock▲DDRClockStructure,1ClkPeriod:2*UI▲ClockBurstalwayscontainsanevennumberoftransition▲ClockcanalsorunwhileD0isinLPmode(especiallyVideomode)■Ex)500Mbps▲Freq:250Mhz,1ClkPeriod:4ns,IU=2ns,16/59HSMode-ClocktoData■DatatoClockTimingDefinition▲90DegreePhaseShiftCLKtoData▲TheFirstbitofDSIPacketmustbesentatarisingedgeofHSClkDataLaneClockLane17/59HSDTSignalinPracticeVCM=200mVnomVo+:typically~300mVVo-:typically~100mVVdiff(positive)18/59LPSignalingDetailedView■Typically1.2V■TLPX-min:50ns19/59LPDTSignalinPractice2TLPXtypically1.2V20/59DPDNPHYLayerGlobalOperationDataUnitOfD-PHY■MinimumDataUnitis1Byte▲Transmitter-Bytestream-Bitstream▲Receiver-Bitstream-Bytestream■HSLanecanbedifferential1or0■LPLaneonD0canhavefourstate(LP+/-)▲LP00:Bridge,Space▲LP01:HS-Rqst,Mark-0▲LP10:LP-Rqst,Mart-1▲LP11:Stop22/59D-PHYOperationFlowDiagram■LP-11(Stop)State▲Thestartstateofeveryoperation.■MajorThreeTypeModes▲EscapeMode▲HST▲BusTurnAround■PHYStateisdecidedbyLPstate▲HSDT:LP11-LP01-LP00-HSDT-LP-11▲LPDT:LP11-LP10-LP00-EscapeMode-LP11■InCaseofClockLane▲HSTisSupportedforClockSupply23/59EscapeModeOperation■EscapeModeEntry,EscapeModeLeave■EscapeModeCommandsEscapeCommandTypeEntryCommandPattern(Firstbit-LastBitTransmittedD1,D2,D3D0Low-PowerDataTransmissionMode11100001(0x87,LSBFirst)-oUltra-LowPowerModeMode00011110(0x78)ooUndefined-1Mode10011111--U