art-II-Lecture-5-Single-cycle-control-and-datapath

CS1104–ComputerOrganizationPART2:ComputerArchitectureLecture5Single-CycleControlandDatapath2TopicsBuildingadatapathsupportasubsetoftheMIPS-Iinstruction-setAsinglecycleprocessordatapathallinstructionactionsinone(long)cycleAmulticycleprocessordatapatheachinstructionstakesmultiple(shorter)cyclesControl:microprogramming3TheMIPSInstructionFormatsAllMIPSinstructionsare32bitslong.Thethreeinstructionformats:R-typeI-typeJ-typeThedifferentfieldsare:op:operationoftheinstructionrs,rt,rd:thesourceanddestinationregisterspecifiersshamt:shiftamountfunct:selectsthevariantoftheoperationinthe“op”fieldaddress/immediate:addressoffsetorimmediatevaluetargetaddress:targetaddressofthejumpinstructionoptargetaddress026316bits26bitsoprsrtrdshamtfunct0611162126316bits6bits5bits5bits5bits5bitsoprsrtimmediate0162126316bits16bits5bits5bits4DatapathandControlDatapathControlRegistersMemoriesMultiplexorsBusesALUsFSMorMicro-programming5We'rereadytolookatanimplementationoftheMIPSSimplifiedtocontainonly:memory-referenceinstructions:lw,swarithmetic-logicalinstructions:add,sub,and,or,sltcontrolflowinstructions:beq,jGenericImplementation:usetheprogramcounter(PC)tosupplyinstructionaddressgettheinstructionfrommemoryreadregistersusetheinstructiontodecideexactlywhattodoAllinstructionsusetheALUafterreadingtheregistersWhy?memory-reference?arithmetic?controlflow?TheProcessor:Datapath&Control6Abstract/SimplifiedView:Twotypesoffunctionalunits:elementsthatoperateondatavalues(combinational)elementsthatcontainstate(sequential)MoreImplementationDetailsRegistersRegister#DataRegister#DatamemoryAddressDataRegister#PCInstructionALUInstructionmemoryAddress7Unclockedvs.ClockedClocksusedinsynchronouslogicwhenshouldanelementthatcontainsstatebeupdated?cycletimerisingedgefallingedgeStateElements8Theset-reset(SR)latchoutputdependsonpresentinputsandalsoonpastinputsAnunclockedstateelementRSQQTruthtable:RSQ00Q01110011?statechange9Outputisequaltothestoredvalueinsidetheelement(don'tneedtoaskforpermissiontolookatthevalue)Changeofstate(value)isbasedontheclockLatches:whenevertheinputschange,andtheclockisassertedFlip-flop:statechangesonlyonaclockedge(edge-triggeredmethodology)Aclockingmethodologydefineswhensignalscanbereadandwritten—wouldn'twanttoreadasignalatthesametimeitwasbeingwrittenLatchesandFlip-flops10Twoinputs:thedatavaluetobestored(D)theclocksignal(C)indicatingwhentoread&storeDTwooutputs:thevalueoftheinternalstate(Q)andit'scomplementD-latchQCD_QDCQ11Dflip-flopOutputchangesonlyontheclockedgeQQ_QQ_QDlatchDCDlatchDDCCDCQ12OurImplementationAnedgetriggeredmethodologyTypicalexecution:readcontentsofsomestateelements,sendvaluesthroughsomecombinationallogic,writeresultstooneormorestateelementsClockcycleStateelement1CombinationallogicStateelement2133-ported:onewrite,tworeadportsRegisterFileReadreg.#1Readreg.#2Writereg.#Readdata1Readdata2WriteWritedata14Registerfile:readportsMuxRegister0Register1Registern–1RegisternMuxReaddata1Readdata2Readregisternumber1Readregisternumber2Implementationofthereadports•RegisterfilebuiltusingDflip-flops15Registerfile:writeportNote:westillusetherealclocktodeterminewhentowriten-to-1decoderRegister0Register1Registern–1CCDDRegisternCCDDRegisternumberWriteRegisterdata01n–1n16SimpleImplementationIncludethefunctionalunitsweneedforeachinstructionWhydoweneedthisstuff?PCInstructionmemoryInstructionaddressInstructiona.Instructionmemoryb.ProgramcounterAddSumc.AdderALUcontrolRegWriteRegistersWriteregisterReaddata1Readdata2Readregister1Readregister2WritedataALUresultALUDataDataRegisternumbersa.Registersb.ALUZero55531632Signextendb.Sign-extensionunitMemReadMemWriteDatamemoryWritedataReaddataa.DatamemoryunitAddress17IncrementingtheProgramCounter(PC)PCInstructionmemoryReadaddressInstruction4AddFetchinginstructionsandincrementingthePC18DatapathforR-typeInstructionsInstructionRegistersWriteregisterReaddata1Readdata2Readregister1Readregister2WritedataALUresultALUZeroRegWriteALUoperation3oprsrtrdshamtfunct0611162126316bits6bits5bits5bits5bits5bitsR-type19DatapathforLoad/StoreInstructionsInstruction1632RegistersWriteregisterReaddata1Readdata2Readregister1Readregister2DatamemoryWritedataReaddataWritedataSignextendALUresultZeroALUAddressMemReadMemWriteRegWriteALUoperation3oprsrtimmediate0162126316bits16bits5bits5bits20DatapathforBranchInstructionsTheALUisusedtoevaluatethebranchconditionandaseparateadderisusedtocomputethebranchtargetaddressasthesumoftheincrementedPCandthesign-extendedlower16bitsoftheinstructionshiftedleftby2bits1632SignextendZeroALUSumShiftleft2TobranchcontrollogicBranchtargetPC+4frominstructiondatapathInstructionAddRegistersWriteregisterReaddata1Readdata2Readregister1Readregister2WritedataRegWriteALUoperation321CombiningDatapathsforMemory&R-typeInstructionsInstructionRegistersWriteregisterReaddata1Readdata2Readregister1Readregister2WritedataALUresultALUZeroRegWriteALUoperation3Instruction1632RegistersWriteregisterReaddata1Readdata2Readregister1Readregister2DatamemoryWritedataReaddataWritedataSigne