译码器应用实例

§5.6译码器•一、定义：输入二进制代码，输出一个特定信号以代表代码原意的组合逻辑电路。•例：设计一个三线、八线译码器100000001110100000001100100000101000100000010000100011000000100010000000101000000000100076543210YYYYYYYYCBACBAYCBAYCBAYCBAYCBAYCBAYCBAYCBAY7__6__5____4__3____2____1______0CBAYCBAYCBAYCBAYCBAYCBAYCBAYCBAY7__6__5____4__3____2____1______0ABC76543210YYYYYYYY二、二极管译码器：ABCVccYABCY776543210yyyyyyyyVccABC三、函数发生器：•用三------八线译码器TTL74138实现Y=AB+BC+CA•TTL74138电路图（输出为负逻辑）__7__6__5__4__3__2__1__0YYYYYYYY210AAA___2___21BACCC____________________5__3__6__7________________________________________________________________________)()()(YYYYCBACBACABCBACBACBACABABCCBBABCAACCABCABCABYY__7__6__5__4__3__2__1__0YYYYYYYY210AAA___2___21BACCCCBA1TTL74138（先化成最小项之和）扩展：(用4块3--8线译码器构成5--32线译码器)__7__6__5__4__3__2__1__0YYYYYYYY210AAA___2___21BACCC__7__6__5__4__3__2__1__0YYYYYYYY__15__14__13__12__11__10__9__8YYYYYYYY__7__6__5__4__3__2__1__0YYYYYYYY210AAA___2___21BACCC__7__6__5__4__3__2__1__0YYYYYYYY210AAA___2___21BACCC__23__22__21__20__19__18__17__16YYYYYYYY__7__6__5__4__3__2__1__0YYYYYYYY210AAA___2___21BACCC__31__30__29__28__27__26__25__24YYYYYYYYA0A1A2A3A424译码器扩展：(用4块3--8线译码器构成5--32线译码器)__7__6__5__4__3__2__1__0YYYYYYYY210AAA___2___21BACCC__7__6__5__4__3__2__1__0YYYYYYYY__15__14__13__12__11__10__9__8YYYYYYYY__7__6__5__4__3__2__1__0YYYYYYYY210AAA___2___21BACCC__7__6__5__4__3__2__1__0YYYYYYYY210AAA___2___21BACCC__23__22__21__20__19__18__17__16YYYYYYYY__7__6__5__4__3__2__1__0YYYYYYYY210AAA___2___21BACCC__31__30__29__28__27__26__25__24YYYYYYYYA0A1A2A3A4作业：•P1869，13,23，24•第四版：P1489,10,11•自考：P12910•用九块3--8线译码器构成6--64线译码器