搜索
ThisistheTitleoftheBook,eMatterEditionCopyright©2005O’Reilly&Associates,Inc.Allrightsreserved.235Chapter9CHAPTER9CommunicatingwithHardwareAlthoughplayingwithscullandsimilartoysisagoodintroductiontothesoftwareinterfaceofaLinuxdevicedriver,implementingarealdevicerequireshardware.Thedriveristheabstractionlayerbetweensoftwareconceptsandhardwarecircuitry;assuch,itneedstotalkwithbothofthem.Upuntilnow,wehaveexaminedtheinter-nalsofsoftwareconcepts;thischaptercompletesthepicturebyshowingyouhowadrivercanaccessI/OportsandI/OmemorywhilebeingportableacrossLinuxplatforms.Thischaptercontinuesinthetraditionofstayingasindependentofspecifichard-wareaspossible.However,wherespecificexamplesareneeded,weusesimpledigi-talI/Oports(suchasthestandardPCparallelport)toshowhowtheI/Oinstructionsworkandnormalframe-buffervideomemorytoshowmemory-mappedI/O.WechosesimpledigitalI/Obecauseitistheeasiestformofaninput/outputport.Also,theparallelportimplementsrawI/Oandisavailableinmostcomputers:databitswrittentothedeviceappearontheoutputpins,andvoltagelevelsontheinputpinsaredirectlyaccessiblebytheprocessor.Inpractice,youhavetoconnectLEDsoraprintertotheporttoactuallyseetheresultsofadigitalI/Ooperation,buttheunderlyinghardwareisextremelyeasytouse.I/OPortsandI/OMemoryEveryperipheraldeviceiscontrolledbywritingandreadingitsregisters.Mostofthetimeadevicehasseveralregisters,andtheyareaccessedatconsecutiveaddresses,eitherinthememoryaddressspaceorintheI/Oaddressspace.Atthehardwarelevel,thereisnoconceptualdifferencebetweenmemoryregionsandI/Oregions:bothofthemareaccessedbyassertingelectricalsignalsontheaddress,ch09.10715Page235Friday,January21,200510:51AMThisistheTitleoftheBook,eMatterEditionCopyright©2005O’Reilly&Associates,Inc.Allrightsreserved.236|Chapter9:CommunicatingwithHardwarebusandcontrolbus(i.e.,thereadandwritesignals)*andbyreadingfromorwritingtothedatabus.WhilesomeCPUmanufacturersimplementasingleaddressspaceintheirchips,oth-ersdecidedthatperipheraldevicesaredifferentfrommemoryand,therefore,deserveaseparateaddressspace.Someprocessors(mostnotablythex86family)havesepa-ratereadandwriteelectricallinesforI/OportsandspecialCPUinstructionstoaccessports.Becauseperipheraldevicesarebuilttofitaperipheralbus,andthemostpopularI/Obusesaremodeledonthepersonalcomputer,evenprocessorsthatdonothaveasep-arateaddressspaceforI/OportsmustfakereadingandwritingI/Oportswhenaccessingsomeperipheraldevices,usuallybymeansofexternalchipsetsorextracir-cuitryintheCPUcore.Thelattersolutioniscommonwithintinyprocessorsmeantforembeddeduse.Forthesamereason,LinuximplementstheconceptofI/Oportsonallcomputerplatformsitrunson,evenonplatformswheretheCPUimplementsasingleaddressspace.Theimplementationofportaccesssometimesdependsonthespecificmakeandmodelofthehostcomputer(becausedifferentmodelsusedifferentchipsetstomapbustransactionsintomemoryaddressspace).EveniftheperipheralbushasaseparateaddressspaceforI/Oports,notalldevicesmaptheirregisterstoI/Oports.WhileuseofI/OportsiscommonforISAperiph-eralboards,mostPCIdevicesmapregistersintoamemoryaddressregion.ThisI/Omemoryapproachisgenerallypreferred,becauseitdoesn’trequiretheuseofspecial-purposeprocessorinstructions;CPUcoresaccessmemorymuchmoreefficiently,andthecompilerhasmuchmorefreedominregisterallocationandaddressing-modeselectionwhenaccessingmemory.I/ORegistersandConventionalMemoryDespitethestrongsimilaritybetweenhardwareregistersandmemory,aprogram-meraccessingI/OregistersmustbecarefultoavoidbeingtrickedbyCPU(orcom-piler)optimizationsthatcanmodifytheexpectedI/Obehavior.ThemaindifferencebetweenI/OregistersandRAMisthatI/Ooperationshavesideeffects,whilememoryoperationshavenone:theonlyeffectofamemorywriteisstoringavaluetoalocation,andamemoryreadreturnsthelastvaluewrittenthere.BecausememoryaccessspeedissocriticaltoCPUperformance,theno-side-effectscasehasbeenoptimizedinseveralways:valuesarecachedandread/writeinstruc-tionsarereordered.*Notallcomputerplatformsuseareadandawritesignal;somehavedifferentmeanstoaddressexternalcir-cuits.Thedifferenceisirrelevantatsoftwarelevel,however,andwe’llassumeallhavereadandwritetosim-plifythediscussion.,ch09.10715Page236Friday,January21,200510:51AMThisistheTitleoftheBook,eMatterEditionCopyright©2005O’Reilly&Associates,Inc.Allrightsreserved.I/OPortsandI/OMemory|237ThecompilercancachedatavaluesintoCPUregisterswithoutwritingthemtomemory,andevenifitstoresthem,bothwriteandreadoperationscanoperateoncachememorywithouteverreachingphysicalRAM.Reorderingcanalsohappenbothatthecompilerlevelandatthehardwarelevel:oftenasequenceofinstructionscanbeexecutedmorequicklyifitisruninanorderdifferentfromthatwhichappearsintheprogramtext,forexample,topreventinterlocksintheRISCpipeline.OnCISCprocessors,operationsthattakeasignificantamountoftimecanbeexe-cutedconcurrentlywithother,quickerones.Theseoptimizationsaretransparentandbenignwhenappliedtoconventionalmem-ory(atleastonuniprocessorsystems),buttheycanbefataltocorrectI/Oopera-tions,becausetheyinterferewiththose“sideeffects”thatarethemainreasonwhyadriveraccessesI/Oregisters.Theprocessorcannotanti