VHDL——如何写简单的testbench

弄了好长时间vhdl，一直对testbench很迷惑。前几天静下心来好好看了下资料，终于会写简单的testbench了。六进制计数器的代码[c-sharp]viewplaincopy1.libraryieee;2.useieee.std_logic_1164.all;3.useieee.std_logic_arith.all;4.--useieee.std_logic_unsigned.all;5.6.entitycnt6is7.port8.(clr,en,clk:instd_logic;9.q:outstd_logic_vector(2downto0)10.);11.endentity;12.13.architecturertlofcnt6is14.signaltmp:std_logic_vector(2downto0);15.begin16.process(clk)17.--variableq6:integer;18.begin19.if(clk'eventandclk='1')then20.if(clr='0')then21.tmp=000;22.elsif(en='1')then23.if(tmp=101)then24.tmp=000;25.else26.tmp=unsigned(tmp)+'1';27.endif;28.endif;29.endif;30.q=tmp;31.--qa=q(0);32.--qb=q(1);33.--qc=q(2);34.endprocess;35.endrtl;六进制计数器testbench的代码[c-sharp]viewplaincopy1.libraryieee;2.useieee.std_logic_1164.all;3.4.entitycnt6_tbis5.endcnt6_tb;6.7.architecturertlofcnt6_tbis8.componentcnt69.port(10.clr,en,clk:instd_logic;11.q:outstd_logic_vector(2downto0)12.);13.endcomponent;14.15.signalclr:std_logic:='0';16.signalen:std_logic:='0';17.signalclk:std_logic:='0';18.signalq:std_logic_vector(2downto0);19.20.constantclk_period:time:=20ns;21.begin22.instant:cnt6portmap23.(24.clk=clk,en=en,clr=clr,q=q25.);26.clk_gen:process27.begin28.waitforclk_period/2;29.clk='1';30.waitforclk_period/2;31.clk='0';32.endprocess;33.34.clr_gen:process35.begin36.clr='0';37.waitfor30ns;38.clr='1';39.wait;40.endprocess;41.42.en_gen:process43.begin44.en='0';45.waitfor50ns;46.en='1';47.wait;48.endprocess;49.endrtl;其实testbench也有自己固定的一套格式，总结如下：[c-sharp]viewplaincopy1.--测试平台文件(testbench)的基本结构2.libraryieee;3.useieee.std_logic_1164.all;4.5.entitytest_benchis--测试平台文件的空实体（不需要端口定义)6.7.endtest_bench;8.9.architecturetb_behavioroftest_benchis10.11.componententity_under_test--被测试元件的声明12.port(13.list-of-ports-theri-types-and-modes14.);15.endcomponent;16.17.begin18.instantiation:entity_under_testportmap19.(20.port-associations21.);22.23.process()--产生时钟信号24.……25.endprocess;26.27.process()--产生激励源28.……29.endprocess;30.endtb_behavior;31.32.-------------------------------------------------------------------33.--简单计数程序源码34.libraryieee;35.useieee.std_logic_1164.all;36.useieee.std_logic_unsigned.all;37.useieee.std_logic_unsigned.all;38.39.entitysim_counteris40.port(41.clk:instd_logic;42.reset:instd_logic;43.count:outstd_logic_vector(3downto0)44.);45.endentity;46.47.architecturebehavioralofsim_counteris48.49.signaltemp:std_logic_vector(3downto0);50.51.begin52.process(clk,reset)53.begin54.ifreset='1'then55.temp=0000;56.elsifclk'eventandclk='1'then57.temp=temp+1;58.endif;59.endprocess;60.count=temp;61.endbehavioral;62.63.-------------------------------------------------------------------64.--简单计数程序，测试文件代码(testbench)65.libraryieee;66.useieee.std_logic_1164.all;67.useieee.std_logic_unsigned.all;68.useieee.numeric_std.all;69.70.entitycounter_tb_vhdis--测试平台实体71.endcounter_tb_vhd;72.73.architecturebehaviorofcounter_tb_vhdis74.--被测试元件（DUT）的声明75.componentsim_counter76.port(77.clk:instd_logic;78.reset:instd_logic;79.count:outstd_logic_vector(3downto0)80.);81.endcomponent;82.--输入信号83.signalclk:std_logic:='0';84.signalreset:std_logic:='0';85.--输出信号86.signalcount:std_logic_vector(3downto0);87.88.constantclk_period:time:=20ns;--时钟周期的定义89.90.begin91.dut:sim_counterportmap(92.clk=clk,reset=reset,counter=counter93.);94.clk_gen:process95.begin96.clk='1';97.waitforclk_period/2;98.clk='0';99.waitforclk_period/2;100.endprocess;101.102.tb:process--激励信号103.begin104.waitfor20ns;105.reset='1';106.waitfor20ns;107.reset='0';108.waitfor200ns;109.wait;--willwaitforever;110.endprocess;111.end;112.113.114.--激励信号的产生方式115.--1.以一定的离散时间间隔产生激励信号的波形116.--2.基于实体的状态产生激励信号，也就是说基于实体的输出响应产生激励信号117.118.--两种常用的复位信号119.--1.周期性的激励信号，如时钟120.--2.时序变化的激励型号，如复位121.122.--eg.产生不对称时钟信号123.w_clk='0'afterperiod/4whenw_clk='1'else124.'1'after3*period/4whenw_clk='0'else125.'0';126.127.--eg.产生堆成时钟信号，process语句128.clk_gen1:process129.constanclk_period:=40ns;130.begin131.clk='1';132.waitforclk_period/2;133.clk='0';134.waitforclk_period/2;135.endprocess;如果自己不想写这些testbench的这些固定格式，可以在quartus里自动生成testbench文件的模板，然后往里面写信号就行了步骤：processing-start-starttestbenchtemplatewrite这里需要注意的是要在仿真选项里选择一个仿真工具，然后才会生成testbench自动生成的testbench模板格式如下：[c-sharp]viewplaincopy1.--Copyright(C)1991-2008AlteraCorporation2.--YouruseofAlteraCorporation'sdesigntools,logicfunctions3.--andothersoftwareandtools,anditsAMPPpartnerlogic4.--functions,andanyoutputfilesfromanyoftheforegoing5.--(includingdeviceprogrammingorsimulationfiles),andany6.--associateddocumentationorinformationareexpresslysubject7.--tothetermsandconditionsoftheAlteraProgramLicense8.--SubscriptionAgreement,AlteraMegaCoreFunctionLicense9.--Agreement,orotherapplicablelicenseagreement,including,10.--withoutlimitation,thatyouruseisforthesolepurposeof11.--programminglogicdevicesmanufacturedbyAlteraandsoldby12.--Alteraoritsauthorizeddistributors.Pleaserefertothe13.--applicableagreementforfurtherdetails.14.15.--***************************************************************************16.--ThisfilecontainsaVhdltestbenchtemplatethatisfreelyeditableto17.-