Jitter-Tolerance06

TrendsinSignalIntegritySeptember,2006Page1TrendsinSignalIntegrityTestParametricTestforHigh-SpeedSerialTechnologiesMichaelReserRainerPlitschkaAgilentTechnologiesHighSpeedDigitalTestTrendsinSignalIntegritySeptember,2006Page2Agenda•TrendandChallengesTestingHigh-SpeedSerialTechnologies•TrendsinHigh-SpeedSerialMarkets•NewChallengesforDesigners•PhysicalLayerTestChallenges•ReceiverToleranceTesting•WhatdoStandardsrequire•TheImportanceoftheReceiver•HowtoimplementJitterEmulation•Agilent’sStrategytoAddresstheNewRequirementsTrendsinSignalIntegritySeptember,2006Page3HighSpeedMarketSegments&TechnologiesSpeed(Gb/s)ComputingEnterprisePublicNetwork0.11.010.040.0AccessMetroProcessorBusMemoryBusCommun-IcationsBusSANLANFront-SideBusPCIExpress-I/II2xFC4xFC8xFC1GEthernetSONETOC-3SONETOC-12SONETOC-48SONETOC-192SONETOC-768Hyper-transport10xFCSATAIIRapidIOFBD-I10GEthernetCEI6GCEI11GHotmarketsPeripheralBusLongHaulFBD-IISATAIIIG-PONE-PONTrendsinSignalIntegritySeptember,2006Page4TrendsinthecomputingenvironmentSerialbussesarebecomingmainstreamAsdataratesgoto3,5,and6Gb/sandbeyond,technicalchallengesareincreasingdisproportionately.•PCIExpressat2.5goingto5Gb/s•SATA/SASat1.5,movesto3and6Gb/s•FBDat4.8goingto9.8Gb/s•CEIdefiningtestsfor6and11Gb/s•Externalcommunicationsforcomputers:–VariousEthernetstandardsto10Gb/s–FibreChannelto10Gb/sTrendsinSignalIntegritySeptember,2006Page5PhysicallayertestingtrendsManyplayers/vendors:TestsandspecsdesignedtomaximizeinteroperabilityVolumeproduction:Avoidhigh-speedtestbyminimizingsensitivitytomanufacturingvariations•HeavyburdenonR&Dtogetitright•Expertiseontheentiresystem(TX/Channel/RX)•Designchangeinoneareamustbevalidatedversusothers•Typicaldigitalengineertoolboxrunningoutofsteam•RequiredJittertestsaretimeconsumingandcomplexTrendsinSignalIntegritySeptember,2006Page6ThenewcommunicationssystemAbusisnowtobeviewedasacommunicationssystemeventhoughspansaremeasuredininchesorcentimetersRxlatchDLLRxPLLChannelTxlatchTxPLLchannelRefclkTransmitterReceiverDataInDataOutGerryTalbot,AMD–DesignConEast2005TrendsinSignalIntegritySeptember,2006Page7Low-costchannelsbecomelossyanddispersiveAChannelrequiresaccuratecharacterizationforimpedanceandtransmissioncharacteristicsincludingequalizationandinteractionswithTXandRXTDRandVNAcharacterizethechannelaloneTDRandVNAcharacterizethechannelaloneRxlatchDLLRxPLLChannelTxlatchTxPLLchannelRefclkTransmitterReceiverDataInDataOutTrendsinSignalIntegritySeptember,2006Page8RxlatchDLLRxPLLChannelTxlatchTxPLLchannelRefclkTransmitterReceiverDataInDataOutTransmittersmustcompensateforlow-costcablesandboardsPre-emphasizedsignalanalysis(optimizedsignalversuschannelperformance),precisionwaveformcharacterizationforcomplianceToolsavailabletodayforcompletesolutionToolsavailabletodayforcompletesolutionTrendsinSignalIntegritySeptember,2006Page9RxlatchDLLRxPLLChannelTxlatchTxPLLchannelRefclkTransmitterReceiverDataInDataOutReceiversmusttoleratedegradedsignalsPrecisely“impaireddatastreams”arerequiredtoverifyreceiverrobustness.Calibratedcompositionofvarioustypesofjitter(RJ,PJ,BUJ,ISI,SI)isrequiredtogeneratereal-worldstressBERTsareofferingcompleteJitterToleranceTestcapabilitiesinonebox.Opportunitytoreducecomplexityandautomatetesting.BERTsareofferingcompleteJitterToleranceTestcapabilitiesinonebox.Opportunitytoreducecomplexityandautomatetesting.SSmmaarrtteessttCharacterizationCharacterizationTrendsinSignalIntegritySeptember,2006Page10Systemsmusttoleratelow-costclocksourcesPhasenoiseanalysiscomplementsjitteranalysisforclockcharacterization21stharmonicSSCfundamentalCurrentlyaverydifficultmeasurement.OpportunityforPLLcharacterizationtechniquesusingphasenoiseapproachCurrentlyaverydifficultmeasurement.OpportunityforPLLcharacterizationtechniquesusingphasenoiseapproachRxlatchCDRRxPLLChannelTxlatchTxPLLchannelRefclkTransmitterReceiverDataInDataOutTrendsinSignalIntegritySeptember,2006Page11EmergingtestrequirementsWhatisneeded:•AbilitytoeasilyanalyzeallaspectsoftheTx/Ch/Rx/RefClkandtreatthemasacompletecommunicationssystem,ratherthanindividualcomponents.•Efficiency–providetherighttoolsettogettofastandaccuratetestresultsdespitetheoverallcomplexityofSignalIntegrityandtheJittertopic.•Easeofuse-letengineersfocusonanalyzingtheirdesignsratherthanlearninghowtousetestequipment.•Confidenceinmeasurementresults-repeatabilityfromonetestsystemtothenext.•Accurate,complete&affordablemeasurementcapabilities.TrendsinSignalIntegritySeptember,2006Page12Agenda•TrendandChallengesTestingHigh-SpeedSerialTechnologies•TrendsinHigh-SpeedSerialMarkets•NewChallengesforDesigners•PhysicalLayerTestChallenges•ReceiverToleranceTesting•WhatdoStandardsrequire•TheImportanceoftheReceiver•HowtoimplementJitterEmulation•Agilent’sStrategytoAddresstheNewRequirementsTrendsinSignalIntegritySeptember,2006Page13Themostneglectedtopic:theRXinputWheretousetheBERT?RXTXcoreDeviceunderTestDUTInOutTXTest:StimulatewithanyPatternGeneratororbuilt-inBISTMeasurewithScope(real-time,sampler),BERTAnalyzerRXTXLoop-backDeviceunderTestDUTInOutRXTest:StimulatewithBERTGenerator(anygeneratorwit