VHDL电路设计例代码

【例3-1】2选1多路选择器程序。（P31）LIBRARYIEEE;--IEEE库使用说明语句USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21IS--实体说明部分PORT(a,b:INSTD_LOGIC;s:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux21;ARCHITECTUREmux21aOFmux21IS--结构体说明部分BEGINPROCESS(a,b,s)BEGINIFs='0'THENy=a;ELSEy=b;ENDIF;ENDPROCESS;ENDARCHITECTUREmux21a;【例3-2】有类属说明的2输入与非门的实体描述。（P33）ENTITYnand2ISGENERIC(t_rise:TIME:=2ns;t_fall:TIME:=1ns)PORT(a:INBIT;b:INBIT;s:OUTBIT);ENDENTITYnand2;【例3-3】n输入与非门的实体描述：（P33）ENTITYnand_nISGENERIC(n:INTEGER);PORT(a:INSTD_LOGIC_VECTOR(n-1DOWNTO0);s:OUTSTD_LOGIC);ENDENTITYnand_n;例3-4】半加器的完整VHDL描述，其中x、y为加数与被加数，s为和信号，c为进位信号。（P36）ENTITYhalf_adderISPORT(x,y:INBIT;s:INBIT;c:OUTBIT);ENDENTITYhalf_adder;ARCHITECTUREdataflowOFhalf_adderISBEGINs=xXORy;c=xANDy;ENDARCHITECTUREdataflow;【例3-5】2选1多路选择器的行为描述程序。（P37）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21ISPORT(a,b:INSTD_LOGIC;s:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux21;ARCHITECTUREbehavOFmux21ISBEGINPROCESS(a,b,s)BEGINIFs='0'THENy=a;ELSEy=b;ENDIF;ENDPROCESS;ENDARCHITECTUREbehav;【例3-6】2选1多路选择器数据流描述程序。（P36）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21ISPORT(a,b:INSTD_LOGIC;s:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux21;ARCHITECTUREdataflowOFmux21ISBEGINy=(aAND(NOTs))OR(bANDs);ENDARCHITECTUREdataflow;【例3-7】2选1多路选择器结构描述程序。（P37）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYand21ISPORT(i0,i1:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDENTITYand21;ARCHITECTUREoneOFand21ISBEGINq=i0ANDi1;ENDARCHITECTUREone;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYor21ISPORT(i0,i1:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDENTITYor21;ARCHITECTUREoneOFor21ISBEGINq=i0ORi1;ENDARCHITECTUREone;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYinv21ISPORT(i0:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDENTITYinv21;ARCHITECTUREoneOFinv21ISBEGINq=(NOTi0);ENDARCHITECTUREone;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21ISPORT(a,b:INSTD_LOGIC;s:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux21;ARCHITECTUREstructOFmux21ISCOMPONENTand21PORT(i0,i1:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTor21PORT(i0,i1:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTinv21PORT(i0:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALtmp1,tmp2,tmp3:STD_LOGIC;BEGINu1:and21PORTMAP(b,s,tmp1);u2:inv21PORTMAP(s,tmp2);u3:and21PORTMAP(a,tmp2,tmp3);u4:or21PORTMAP(tmp1,tmp3,y);ENDARCHITECTUREstruct;【例3-8】半加器的混合描述程序。（P37）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYxor21ISPORT(i0,i1:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDENTITYxor21;ARCHITECTUREbehavOFxor21ISBEGINq=i0XORi1;ENDARCHITECTUREbehav;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYhalf_adderISPORT(a,b:INSTD_LOGIC;c,s:OUTSTD_LOGIC);ENDENTITYhalf_adder;ARCHITECTUREmixOFhalf_adderISCOMPONENTxor21ISPORT(i0,i1:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDCOMPONENT;BEGINc=aANDb;u1:xor21PORTMAP(a,b,s);ENDARCHITECTUREmix;【例3-9】打开一个字符文件，读出文件中的内容并关闭文件。（P51）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYreadfileISPORT(cs:INSTD_LOGIC;c:OUTCHARACTER);ENDENTITYreadfile;ARCHITECTUREread1OFreadfileISBEGINPROCESS(cs)TYPEchar_fileISFILEOFCHARACTER;FILEcfile:char_file;VARIABLEi:INTEGER:=0;BEGINIF(cs='1')THENFILE_OPEN(cfile,f:/leifr/testfile.asc,READ_MODE);WHILENOTENDFILE(cfile)LOOPREAD(cfile,c);i:=i+1;ENDLOOP;FILE_CLOSE(cfile);ELSEc='-';ENDIF;ENDPROCESS;ENDARCHITECTUREread1;【例4-1】WAIT语句示例程序。（P65）cwait1：PROCESSBEGINy=(aANDb)OR(mXORt);z=cNANDd;WAIT;--无限等待ENDPROCESScwait1;【例4-2】WAITFOR语句示例程序。（65）cwait2：PROCESSBEGINy=(aANDb)OR(mXORt);z=cNANDd;WAITFOR10*(ct1+ct2);--等待由该表达式计算的时间ENDPROCESScwait2;【例4-3】WAITON语句示例程序（二选一选择器）。（P66）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux2_1ISPORT(data0,data1:INSTD_LOGIC;sel:INSTD_LOGIC;q:OUTSTD_LOGIC);ENDmux2_1;ARCHITECTUREbehavioralOFmux2_1ISSIGNALtemp1,temp2,temp3:STD_LOGIC;BEGINcwait3：PROCESSBEGINtemp1=data0ANDsel;temp2=data1AND(NOTsel);temp3=temp1ORtemp2;q=temp3;WAITONdata0,data1,q;ENDPROCESScwait3;ENDbehavioral;【例4-4】WAITON语句和PROCESS语句中所使用的敏感信号列表的对比。（P67）ARCHITECTUREbehavioralOFmux2_1ISSIGNALtemp1,temp2,temp3:STD_LOGIC;BEGINcwait4：PROCESS(data0,data1,q)BEGINtemp1=data0ANDsel;temp2=data1AND(NOTsel);temp3=temp1ORtemp2;q=temp3;ENDPROCESScwait4;ENDbehavioral;【例4-5】WAITUNTIL语句示例程序。（P67）ARCHITECTUREbehavioralOFexample_waituntilISSIGNALtemp:INTEGER;BEGINcwait5：PROCESSBEGINWAITUNTIL((temp+5)=20);--该表达式是布尔表达式ENDPROCESScwait5;ENDbehavioral;【例4-6】多条件WAIT语句的示例程序。（P68）cwait6：PROCESSBEGIN--多条件WAIT语句WAITONdata0,data1,qUNTIL((temp+5)=20)FOR34ns;ENDPROCESScwait6;【例4-7】信号代入语句示例程序。（P68）ARCHITECTUREbehavioralOFexample_dairuISSIGNALa,b,c,d,e,f:STD_LOGIC;SIGNALtemp0,temp1,temp2,temp3,temp4,temp5:STD_LOGIC;BEGINcdairu：PROCESSBEGINtemp0=aNANDb;--与非temp1=cNORd;--或非temp2=eXORfAFTER5ns;--异或门延迟temp3=(aNANDb)NOR(cNANDd);temp4=(cORd)NAND(eORf);temp5=aXORbXORcXORdXOReXORf;ENDPROCESScdairu;ENDbehavioral;【例4-8】变量赋值语句示例程序。（P69）ARCHITECTUREbehavioralOFexample_fuzhiISCONSTANTcvolt:REAL:=3.3;--定义常数CONSTANTccurrent:REAL:=4.0;VARIABLEtemp0,temp1:REAL;--定义变量VARIABLEtemp2,temp3:INTEGERRANGE0TO255:=10;VARIABLEtemp4:STD_LOGIC_VECTOR(3DOWNTO0);VARIABLEtemp5:STD_LOGIC;SIGNALa:STD_LOGIC;--定义信号SIGNALb:REAL;SIGNALc:INTEGER;SIGNALd:STD_LOGIC_VECTOR(3DOWNTO0);BEGINcfuzhi：PRO