TLV2211

TLV2211,TLV2211YAdvancedLinCMOSRAIL-TO-RAILMICROPOWERSINGLEOPERATIONALAMPLIFIERSSLOS156B–MAY1996–REVISEDJANUARY19971POSTOFFICEBOX655303•DALLAS,TEXAS75265OutputSwingIncludesBothSupplyRailsLowNoise...21nV/√HzTypatf=1kHzLowInputBiasCurrent...1pATypVeryLowPower...13μAPerChannelTypCommon-ModeInputVoltageRangeIncludesNegativeRailWideSupplyVoltageRange2.7Vto10VAvailableintheSOT-23PackageMacromodelIncludeddescriptionTheTLV2211isasingleoperationalamplifiermanufacturedusingtheTexasInstrumentsAdvancedLinCMOSprocess.Thesedevicesareoptimizedandfullyspecifiedforsingle-supply3-Vand5-Voperation.Forthislow-voltageoperationcombinedwithmicropowerdissipationlevels,theinputnoisevoltageperformancehasbeendramaticallyimprovedusingoptimizeddesigntechniquesforCMOS-typeamplifiers.Anotheraddedbenefitisthattheseamplifiersexhibitrail-to-railoutputswing.TheoutputdynamicrangecanbeextendedusingtheTLV2211withloadsreferencedmidwaybetweentherails.Thecommon-modeinputvoltagerangeiswiderthantypicalstandardCMOS-typeamplifiers.Totakeadvantageofthisimprovementinperformanceandtomakethisdeviceavailableforawiderrangeofapplications,VICRisspecifiedwithalargermaximuminputoffsetvoltagetestlimitof±5mV,allowingaminimumof0to2-Vcommon-modeinputvoltagerangefora3-Vpowersupply.AVAILABLEOPTIONSTAVIOmaxAT25°CPACKAGEDDEVICESSYMBOLCHIPFORMTAVIOmaxAT25°CSOT-23(DBV)†SYMBOL(Y)0°Cto70°C3mVTLV2211CDBVVACCTLV2211Y–40°Cto85°C3mVTLV2211IDBVVACITLV2211Y†TheDBVpackageavailableintapeandreelonly.TheAdvancedLinCMOSprocessusesasilicon-gatetechnologytoobtaininputoffsetvoltagestabilitywithtemperatureandtimethatfarexceedsthatobtainableusingmetal-gatetechnology.Thistechnologyalsomakespossibleinput-impedancelevelsthatmeetorexceedlevelsofferedbytop-gateJFETandexpensivedielectric-isolateddevices.TheTLV2211,exhibitinghighinputimpedanceandlownoise,isexcellentforsmall-signalconditioningforhigh-impedancesourcessuchaspiezoelectrictransducers.Becauseofthelowpowerdissipationlevelscombinedwith3-Voperation,thesedevicesworkwellinhand-heldmonitoringandremote-sensingapplications.Inaddition,therail-to-railoutputfeaturewithsingleorsplitsuppliesmakesthesedevicesexcellentchoiceswheninterfacingdirectlytoanalog-to-digitalconverters(ADCs).AllofthesefeaturescombinedwithitstemperatureperformancemaketheTLV2211idealforremotepressuresensors,temperaturecontrol,activevoltage-resistive(VR)sensors,accelerometers,hand-heldmetering,andmanyotherapplications.Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.DBVPACKAGE(TOPVIEW)54312IN–VDD–/GNDIN+VDD+OUTPRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsofTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters.Copyright1997,TexasInstrumentsIncorporatedAdvancedLinCMOSisatrademarkofTexasInstrumentsIncorporated.TLV2211,TLV2211YAdvancedLinCMOSRAIL-TO-RAILMICROPOWERSINGLEOPERATIONALAMPLIFIERSSLOS156B–MAY1996–REVISEDJANUARY19972POSTOFFICEBOX655303•DALLAS,TEXAS75265description(continued)Thedeviceinputsandoutputsaredesignedtowithstanda100-mAsurgecurrentwithoutsustaininglatch-up.Inaddition,internalESD-protectioncircuitspreventfunctionalfailuresupto2000VastestedunderMIL-PRF-38535;however,careshouldbeexercisedwhenhandlingthesedevicesasexposuretoESDmayresultindegradationofthedeviceparametricperformance.AdditionalcareshouldbeexercisedtopreventVDD+supply-linetransientsunderpoweredconditions.Transientsofgreaterthan20VcantriggertheESD-protectionstructure,inducingalow-impedancepathtoVDD–/GND.Shouldthisconditionoccur,thesustainedcurrentsuppliedtothedevicemustbelimitedto100mAorless.Failuretodosocouldresultinalatchedconditionanddevicefailure.TLV2211,TLV2211YAdvancedLinCMOSRAIL-TO-RAILMICROPOWERSINGLEOPERATIONALAMPLIFIERSSLOS156B–MAY1996–REVISEDJANUARY19973POSTOFFICEBOX655303•DALLAS,TEXAS75265TLV2211YchipinformationThischip,whenproperlyassembled,displayscharacteristicssimilartotheTLV2211C.Thermalcompressionorultrasonicbondingmaybeusedonthedoped-aluminumbondingpads.Thischipmaybemountedwithconductiveepoxyoragold-siliconpreform.BONDINGPADASSIGNMENTSCHIPTHICKNESS:10MILSTYPICALBONDINGPADS:4×4MILSMINIMUMTJmax=150°CTOLERANCESARE±10%.ALLDIMENSIONSAREINMILS.PIN(2)ISINTERNALLYCONNECTEDTOBACKSIDEOFCHIP.+–OUTIN+IN–VDD+(5)(1)(3)(4)(2)VDD–/GND40(3)(2)(1)(5)(4)32TLV2211,TLV2211YMICROPOWERSINGLEOPERATIONALAMPLIFIERSSLOS156B–MAY1996–REVISEDJANUARY1997TemplateReleaseDate:7–11–94AdvancedLinCMOSRAIL-TO-RAIL4POSTOFFICEBOX655303DALLAS,TEXAS75265•equivalentschematicQ3Q6Q9Q12Q14Q16Q2Q5Q7Q8Q10Q11D1Q17Q15Q13Q4Q1R5C1VDD+IN+IN–R3R7R1R2OUTVDD–/GNDCOMPONENTCOUNT†TransistorsDiodesResistorsCapacitors236112†IncludesbothamplifiersandallESD,bias,andtrimcircuitryR6C2D2R4TLV2211,TLV2211YAdvancedLinCMOSRAIL-TO-RAILMICROPOWERSINGLEOPERATIONALAMPLIFIERSSLOS156B–MAY1996–REVISEDJANUARY19975POSTOFFICEBOX655303•DALLAS,TEXAS75265absolutemaximumratingsoveroperatingfree-airtemperaturerange(unl