Coding_Style_Guidelines_for_Nextreme-AN01

ApplicationNoteAN-1AN-1(VHDL)_________________________________________42.1.Donotinferlatches_______________________________________________42.1.1.Incomplete‘case’statement(sequentialconditionalsignalassignment)42.1.2.Incomplete‘when’statement(concurrentconditionalsignalassignment)52.1.3.‘if’without‘else’(sequentialconditionalsignalassignment)_________52.1.4.Incompleteresetblock(sequentialconditionalsignalassignment)____62.1.5.Variableusedbeforeassignment_____________________________62.2.Donotinfertri-statebuffers_________________________________________72.2.1.Donotdirectlyinfertri-states(concurrentsignalassignment)________72.2.2.Donotusewired-ANDorwire-OR(concurrentsignalassignment)____72.2.3.Donotassignavaluetoasignalinmorethanoneprocess(sequentialsignalassignment)_______________________________________________82.3.AvoidSimulationversusSynthesismismatches_________________________82.3.1.SensitivityList____________________________________________93.GeneralDesignGuidelines(Verilog)_______________________________________103.1.Donotinferlatches______________________________________________103.1.1.Incomplete‘case’statement(sequentialconditionalsignalassignment)103.1.2.‘if’without‘else’(sequentialconditionalsignalassignment)________103.1.3.Incompleteresetblock(sequentialconditionalsignalassignment)___113.2.Donotinfertri-statebuffers________________________________________113.2.1.Donotdirectlyinfertri-states(concurrentsignalassignment)_______113.2.2.Donotusewired-ANDorwire-OR(concurrentsignalassignment)___113.2.3.Donotassignavaluetoasignalinmorethanonealwaysblock(sequentialsignalassignment)_____________________________________123.3.AvoidSimulationversusSynthesismismatches________________________123.3.1.SensitivityList___________________________________________12CodingStyleGuidelines2://’sNextremeStructuredASICdevices.AdoptingtheserulesensuresthedesigncanbesynthesizedseamlesslytoeASICtechnologyandprovideefficientimplementationresults.Theguidelinesaresortedaccordingtomainsubjects,butmostofthemarerelatedtoothersubjectsaswell.Eachguidelineisplacedinthesectionwhereitsinfluenceismajor,butitcanhaveamarkedimpactonothersectionsaswell.Theguidelinesdescribedinthisdocumentareofdifferentimportance.Theyareclassifiedas:RULE–signifiesahardguideline.ThisguidelineMUSTbefollowed;otherwisethedesigncannotbeimplementedinNextremetechnologyRECOMMENDATION–signifiesarecommendedguideline.Itisunlikelythataproblemcannotbesolvedwithoutviolatingthisguideline.ThisguidelineSHOULDbefollowed.Violatingthisguidelinewillnotresultinanimplementationerror,buttheimplementationmaybesub-optimal.SUGGESTION–signifiesa“gooddesignpractice”guideline.Violatingthisguidelinewillnotresultinanimplementationerrororasub-optimalimplementation.CodingStyleGuidelines4(VHDL)2.1.DonotinferlatchesNextremeStructuredASICdoesnotsupportlatches,howevercertainRTLcodingstylesunintentionallyinferlatches.Thissectiondescribesthesecodingstylesandhowtoavoidthem.2.1.1.Incomplete‘case’statement(sequentialconditionalsignalassignment)Incompletecasestatementsforcethesynthesistooltostorethelastvalue;thereforeinferringlatches.VHDLstd_logicdefinitionhasmultiplelogiclev