专用集成电路实验报告材料56

实用标准文案文档大全专用集成电路实验报告组合逻辑电路特性姓名：学号：班级：指导老师：实用标准文案文档大全一、实验目的1.理解CMOS复杂逻辑门的综合过程及其特性。2.理解加法器的结构。二、实验内容1)利用对偶原理综合CMOS互补门，功能为：01010YAABBC，简述综合过程，画出三极管级原理图。2)一个1bit全加器的逻辑表达式为：SABCi，CoABCiAB；A、B为加法输入，Ci为进位输入，S为和输出，Co为进位输出；为异或操作，+为或操作，为与操作。a)画出2bit全加器的门级原理图；b)通过调整输入的不同位置，下列电路能够实现AND、OR、XOR及其非逻辑的功能，图中的三极管为NMOS。使用多个下列电路实现2bit全加器，画出三极管级原理图。I1I2I3I4I5I6O1O23)设使用0.25um工艺，NMOS管的尺寸为L=0.250um，W=0.375um；PMOS管的尺寸为L=0.250um，W=1.125um。对实验内容1和2的电路进行spice仿真。调整实验内容1的器件尺寸和电源电压，观察门的延时；观察和理解实验内容2中加法器的进位延时。三、实验步骤及过程：1）实用标准文案文档大全图1OrCAD画出的三极管级原理图2)A）图22bit全加器的门级原理图M1MbreakPDM2MbreakPDM3MbreakPDM4MbreakPDM5MbreakPDM6MbreakNDM7MbreakNDM8MbreakNDM9MbreakNDM10MbreakND0VCCB1A1C0A0B0B0C0A0B1A1YU1A74HC08123U2A74HC386123U2B74HC386564U3A74HC08123U4A74HC832123U5A74HC08123U5B74HC08456U6A74HC386123U6B74HC386564U7A74HC832123A1B1A0B0cinSUM1SUM0cout实用标准文案文档大全B)差分传输管逻辑的与和与非逻辑：图3与门（与非门）差分传输管逻辑的或和或非逻辑：图4或门（或非门）差分传输管逻辑的异或和异或非：图5异或门（异或非门）总的2bit全加器的原理图：M11MbreakNM12AND1M13MbreakNM14MbreakNAND1A0!A0AND1!B0!B0M31MbreakNM32OR1M33MbreakNM34MbreakNcout0！cout0AND1！AND1AND2AND2!M11MbreakNM12AND1M13MbreakNM14MbreakNAND1A0!A0AND1!B0!B0实用标准文案文档大全图6差分传输管构成的2bit全加器3）A、调节实验内容1的器件尺寸和电源电压，观察门的延时。这里设定A0为pulse信号，A1为2.5V，其余都为0V，则Y的输出与A0反向，输出波形应该类似于反相器。图3.1输入和输出波形Measure输出文件：M11MbreakNM12AND1M13MbreakNM14MbreakNM15MbreakNM16XOR1M17MbreakNM18MbreakNM19MbreakNM20AND2M21MbreakNM22MbreakNM23MbreakNM24XOR2M25MbreakNM26MbreakNM27MbreakNM28OR2M29MbreakNM30MbreakNM31MbreakNM32OR1M33MbreakNM34MbreakNAND1A0!A0AND1!B0!B0M51MbreakNM52MbreakPD0A0!AVCCA0M53MbreakNM54MbreakPD0A1!A1M55MbreakNM56MbreakPD0B0!B0VCCVCCM57MbreakNM58MbreakPD0B1B1!VCCM59MbreakNM60MbreakPD0cin!cinVCCXOR1XOR1!A0!B0!B0AND2cincin！AND2！cin!cinXOR1XOR1！A0XOR1！XOR1AND2SUM0AND2！M35MbreakNM36AND3M37MbreakNM38MbreakNM39MbreakNM40XOR3M41MbreakNM42MbreakNM43MbreakNM44AND4M45MbreakNM46MbreakNM47MbreakNM48XOR4M49MbreakNM50MbreakNAND3A1A1!AND3!B1B1!XOR3XOR3!B1B1!A1!AND4！cout0！cout0SUM1!coutcout!XOR3！XOR3XOR3！A1SUM1AND4XOR3cout0！cout0AND1！AND1AND2AND2!AND4!AND3AND3!AND4实用标准文案文档大全$DATA1SOURCE='HSPICE'VERSION='U-2003.09'.TITLE'*dai56_1object't1dlayt2dlaytemperalter#6.580e-116.900e-1125.00001.0000t1dlay为输出端下降沿与输出端上升沿的50%——50%延时。t2dlay为输出端上升沿与输出端下降沿的50%——50%延时。程序（网表文件）：*dai56_1object.lib'cmos25_level49.txt'TT.optionspost=2Vccpvcc0dc2.5VVA1A10dc2.5VVB0B00dc0VVB1B10dc0VVC1C10dc0VVinA00pulse(0V2.5V0ps0ps0ps500ps1000ps)mA01A0GNDGNDNMOSL=0.25uW=0.375umB02B0GNDGNDNMOSL=0.25uW=0.375umC03C0GNDGNDNMOSL=0.25uW=0.375umA13A111NMOSL=0.25uW=0.375umB13B122NMOSL=0.25uW=0.375umA0p5A0pvccpvccPMOSL=0.25uW=1.125umA1p5A1pvccpvccPMOSL=0.25uW=1.125umB0p4BO55PMOSL=0.25uW=1.125umB1p4B155PMOSL=0.25uW=1.125u实用标准文案文档大全mC0p3CO44PMOSL=0.25uW=1.125u.measuretrant1dlaytrigV(a0)val=1.25Vtd=0fall=2+targV(3)val=1.25Vtd=0rise=2.measuretrant2dlaytrigV(a0)val=1.25Vtd=0rise=2+targV(3)val=1.25Vtd=0fall=2.tran1ps3ns.probeVinV(3).end接下来调整电源电压，观察门的延时：VCC=1.5V图3.2VCC=1.5V时的输出波形Measure输出文件：$DATA1SOURCE='HSPICE'VERSION='U-2003.09'.TITLE'*dai56_1object't1dlayt2dlaytemperalter#实用标准文案文档大全1.239e-103.85e-1125.00001.0000Vcc=1V图3.3VCC=1V时的输出波形Measure输出文件：$DATA1SOURCE='HSPICE'VERSION='U-2003.09'.TITLE'*dai56_1object't1dlayt2dlaytemperalter#2.682e-102.35e-1125.00001.0000观察结论：当电源电压降低时，门的延时增加。需要特别注意的是measure语句编写时，需要根据输出波形的电压值改变阈值。改变三极管尺寸，观察门的延时：Pmos的沟道宽度Wa)PMOS管均为W=1.125um；b)PMOS管均为W=1.875um；c)PMOS管均为W=3.000um；实用标准文案文档大全图3.4改变Pmos的沟道宽度的输出波形Measure文件：$DATA1SOURCE='HSPICE'VERSION='U-2003.09'.TITLE'*dai56_1object'indexpwct1dlayt2dlaytemperalter#1.00001.125e-062.658e-106.900e-1125.00001.00002.00001.875e-062.526e-101.112e-1025.00001.00003.00003.000e-062.436e-101.761e-1025.00001.0000这里在网表文件中运用了data语句。观察结论：Pmos的沟道宽度变宽后门的传输延时增大。实用标准文案文档大全用对偶原理综合CMOS互补门设计的2bit全加器的进位延时：验证全加器逻辑关系：图3.5验证全加器逻辑关系由上至下依次为A1A0，B1B0,V10(sum1),V6(sum0),cout1.电压值为：A1=B1=0V，A0=B0=2.5V，sum1=2.5V，sum0=0V，cout1=0V。即01+01=10，进位为0.全加器逻辑正确。程序（网表文件）：*dai56_2object.lib'cmos25_level49.txt'TT.optionspost=2.tran1ps15ns.probeV(cout1)V(10)V(6)V(a0).globalpvccvccVccpvcc0dc2.5VV1A00dc2.5VV2A10dc0V实用标准文案文档大全V3B00dc2.5VV4B10dc0VV5cin0dc0V.subcktANDgABYm11AGNDGNDNMOSL=0.25uW=0.375um22B1gndNMOSL=0.25uW=0.375um1p2ApvccpvccPMOSL=0.25uW=1.125um2p2BpvccpvccPMOSL=0.25uW=1.125um3pY2pvccpvccPMOSL=0.25uW=1.125um3Y2GNDGNDNMOSL=0.25uW=0.375u.ends.subcktORgA1B1Y1m11A1GNDGNDNMOSL=0.25uW=0.375um21B1GNDGNDNMOSL=0.25uW=0.375um1p2ApvccpvccPMOSL=0.25uW=1.125um2p1B2pvccPMOSL=0.25uW=1.125um3pY11pvccpvccPMOSL=0.25uW=1.125um3Y11GNDGNDNMOSL=0.25uW=0.375u.ends.subcktxorga2b2y2m01A2aA2pvccpvccPMOSL=0.25uW=1.125um02A2aA2GNDGNDNMOSL=0.25uW=0.375um03B2aB2pvccpvccPMOSL=0.25uW=1.125um04B2aB2GNDGNDNMOSL=0.25uW=0.375um11B2aGNDGNDNMOSL=0.25uW=0.375um22B2GNDGNDNMOSL=0.25uW=0.375u实用标准文案文档大全m3y2A2a1GNDNMOSL=0.25uW=0.375um4y2A22gndNMOSL=0.25uW=0.375um1p4A2pvccpvccPMOSL=0.25uW=1.125um2p4B2pvccpvccPMOSL=0.25uW=1.125um3py2A2a4pvccPMOSL=0.25uW=1.125um4py2B2a4pvccPMOSL=0.25uW=1.125u.endsx1A0B03ANDgx2A0b04XORgx34cin5ANDgx44cin6XORgx535cout0ORgx6A1b17ANDgx7A1b18XORgx88cout09ANDgx98cout010XORgx1079cout1ORg.end