NANYA_NT5DS32M16CS-5T

NT5DS32M16CGNT5DS32M16CSNT5DS64M8CGNT5DS64M8CSNT5DS128M4CGNT5DS128M4CS512MbDDRSDRAMREV1.0Dec20071©NANYATECHNOLOGYCORP.Allrightsreserved.NANYATECHNOLOGYCORP.reservestherighttochangeProductsandSpecificationswithoutnotice.Features•DDR512Mbit,DieC,basedon90nmdesignrules•Doubledataratearchitecture:twodatatransfersperclockcycle•Bidirectionaldatastrobe(DQS)istransmittedandreceivedwithdata,tobeusedincapturingdataatthereceiver•DQSisedge-alignedwithdataforreadsandiscenter-alignedwithdataforwrites•Differentialclockinputs(CKandCK)•Fourinternalbanksforconcurrentoperation•Datamask(DM)forwritedata•DLLalignsDQandDQStransitionswithCKtransitions•CommandsenteredoneachpositiveCKedge;dataanddatamaskreferencedtobothedgesofDQS•Burstlengths:2,4,or8•CASLatency:2.5,3•AutoPrechargeoptionforeachburstaccess•AutoRefreshandSelfRefreshModes•7.8msMaximumAveragePeriodicRefreshInterval•2.5V(SSTL_2compatible)I/O•VDD=VDDQ=2.6V±0.1V(DDR400)•VDD=VDDQ=2.5V±0.2V(DDR333)•RoHScomplianceDescriptionDieCof512MbSDRAMdevicesbasedusingDDRinterface.TheyareallbasedonNanya’s90nmdesignprocess.The512MbDDRSDRAMisahigh-speedCMOS,dynamicrandom-accessmemorycontaining536,870,912bits.Itisinternallyconfiguredasaquad-bankDRAM.The512MbDDRSDRAMusesadouble-data-ratearchitec-turetoachievehigh-speedoperation.Thedoubledataratearchitectureisessentiallya2nprefetcharchitecturewithaninterfacedesignedtotransfertwodatawordsperclockcycleattheI/Opins.Asinglereadorwriteaccessforthe512MbDDRSDRAMeffectivelyconsistsofasingle2n-bitwide,oneclockcycledatatransferattheinternalDRAMcoreandtwocorrespondingn-bitwide,one-half-clock-cycledatatransfersattheI/Opins.Abidirectionaldatastrobe(DQS)istransmittedexternally,alongwithdata,foruseindatacaptureatthereceiver.DQSisastrobetransmittedbytheDDRSDRAMduringReadsandbythememorycontrollerduringWrites.DQSisedge-alignedwithdataforReadsandcenter-alignedwithdataforWrites.The512MbDDRSDRAMoperatesfromadifferentialclock(CKandCK;thecrossingofCKgoinghighandCKgoingLOWisreferredtoasthepositiveedgeofCK).Commands(addressandcontrolsignals)areregisteredateverypositiveedgeofCK.InputdataisregisteredonbothedgesofDQS,andoutputdataisreferencedtobothedgesofDQS,aswellastobothedgesofCK.ReadandwriteaccessestotheDDRSDRAMareburstori-ented;accessesstartataselectedlocationandcontinueforaprogrammednumberoflocationsinaprogrammedsequence.AccessesbeginwiththeregistrationofanActivecommand,whichisthenfollowedbyaReadorWritecom-mand.TheaddressbitsregisteredcoincidentwiththeActivecommandareusedtoselectthebankandrowtobeaccessed.TheaddressbitsregisteredcoincidentwiththeReadorWritecommandareusedtoselectthebankandthestartingcolumnlocationfortheburstaccess.TheDDRSDRAMprovidesforprogrammableReadorWriteburstlengthsof2,4,or8locations.AnAutoPrechargefunc-tionmaybeenabledtoprovideaself-timedrowprechargethatisinitiatedattheendoftheburstaccess.AswithstandardSDRAMs,thepipelined,multibankarchitec-tureofDDRSDRAMsallowsforconcurrentoperation,therebyprovidinghigheffectivebandwidthbyhidingrowpre-chargeandactivationtime.Anautorefreshmodeisprovidedalongwithapower-savingPowerDownmode.AllinputsarecompatiblewiththeJEDECStandardforSSTL_2.AlloutputsareSSTL_2,ClassIIcom-patible.ThefunctionalitydescribedandthetimingspecificationsincludedinthisdatasheetarefortheDLLEnabledmodeofoperation.NT5DS32M16CGNT5DS32M16CSNT5DS64M8CGNT5DS64M8CSNT5DS128M4CGNT5DS128M4CS512MbDDRSDRAMREV1.0Dec20072©NANYATECHNOLOGYCORP.Allrightsreserved.NANYATECHNOLOGYCORP.reservestherighttochangeProductsandSpecificationswithoutnotice.OrderingInformation(Lead-Free)Org.PartNumberPackageSpeedCommentsClock(MHz)CL-tRCD-tRP128Mx4NT5DS128M4CS-5T66pinTSOP-II2003-3-3DDR400NT5DS128M4CS-6K1662.5-3-3DDR333NT5DS128M4CG-5T60ballBGA0.8mmx1.0mmPitch2003-3-3DDR400NT5DS128M4CG-6K1662.5-3-3DDR33364Mx8NT5DS64M8CS-5T66pinTSOP-II2003-3-3DDR400NT5DS64M8CS-6K1662.5-3-3DDR333NT5DS64M8CG-5T60ballBGA0.8mmx1.0mmPitch2003-3-3DDR400NT5DS64M8CG-6K1662.5-3-3DDR33332Mx16NT5DS32M16CS-5T66pinTSOP-II2003-3-3DDR400NT5DS32M16CS-6K1662.5-3-3DDR333NT5DS32M16CG-5T60ballBGA0.8mmx1.0mmPitch2003-3-3DDR400NT5DS32M16CG-6K1662.5-3-3DDR333NT5DS32M16CGNT5DS32M16CSNT5DS64M8CGNT5DS64M8CSNT5DS128M4CGNT5DS128M4CS512MbDDRSDRAMREV1.0Dec20073©NANYATECHNOLOGYCORP.Allrightsreserved.NANYATECHNOLOGYCORP.reservestherighttochangeProductsandSpecificationswithoutnotice.PinConfiguration-400milTSOPII(x4/x8/x16)123456910111213147815161718192021226665646362615857565554536059525150494847464523242544434226274140282930313233393837363534VDDDQ0VDDQNCDQ1VSSQVDDQNCDQ3VSSQNCNCNCDQ2VDDQNCNCVDDNUNCWECASRASCSNCBA0BA1VSSDQ7VSSQNCDQ6VDDQVSSQNCDQ4VDDQNCNCNCDQ5VSSQDQSNCVREFVSSDM*CKCKCKENCA12A11A9VDDNCVDDQNCDQ0VSSQVDDQNCDQ1VSSQNCNCNCNCVDDQNCNCVDDNUNCWECASRASCSNCBA0BA1VSSNCVSSQNCDQ3VDDQVSSQNCDQ2VDDQNCNCNCNCVSSQDQSNCVREFVSSDM*CKCKCKENCA12A11A9A10/APA0A1A2A3VDDA10/APA0A1A2A3VDDA8A7A6A5A4VSSA8A7A6A5A4VSSColumnAddressTableOrganizationColumnAddress128Mbx4A0-A9,A11,A1264Mbx8A0-A9,A1132Mbx16A0-A9*DMisinternallyloadedtomatchDQandDQSidentically.128Mbx464Mbx866-pinPlasticTSOP-II400mil32Mbx16VDDDQ0VDDQDQ1DQ2VSSQVDDQDQ5DQ6VSSQDQ7NCDQ3DQ4VDDQLD